Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach

Stéphane Pouget, Louis-Noël Pouchet, Jason Cong

TL;DR

This work tackles the challenge of automatically selecting HLS pragmas to optimize kernel QoR by introducing NLP-DSE, a non-linear programming framework that targets affine, regular-loop programs. By building an analytical, latency-and-resource model compatible with the Merlin/Vitis toolchain and proving a latency lower bound, the approach enables fast pruning of vast design spaces and efficient pragma optimization. NLP-DSE consistently achieves equal or better QoR than AutoDSE and HARP across numerous benchmarks, often with orders of magnitude faster design-space exploration. The method demonstrates strong potential for practical FPGA development, offering interpretable performance estimates and scalable search, with future work guiding more extensive code transformations beyond pragma insertion. The practical impact lies in dramatically reducing design time while delivering high-quality hardware accelerators for AI, linear algebra, and data-processing kernels.

Abstract

High-Level Synthesis enables the rapid prototyping of hardware accelerators, by combining a high-level description of the functional behavior of a kernel with a set of micro-architecture optimizations as inputs. Such optimizations can be described by inserting pragmas e.g. pipelining and replication of units, or even higher level transformations for HLS such as automatic data caching using the AMD/Xilinx Merlin compiler. Selecting the best combination of pragmas, even within a restricted set, remains particularly challenging and the typical state-of-practice uses design-space exploration to navigate this space. But due to the highly irregular performance distribution of pragma configurations, typical DSE approaches are either extremely time consuming, or operating on a severely restricted search space. This work proposes a framework to automatically insert HLS pragmas in regular loop-based programs, supporting pipelining, unit replication, and data caching. We develop an analytical performance and resource model as a function of the input program properties and pragmas inserted, using non-linear constraints and objectives. We prove this model provides a lower bound on the actual performance after HLS. We then encode this model as a Non-Linear Program, by making the pragma configuration unknowns of the system, which is computed optimally by solving this NLP. This approach can also be used during DSE, to quickly prune points with a (possibly partial) pragma configuration, driven by lower bounds on achievable latency. We extensively evaluate our end-to-end, fully implemented system, showing it can effectively manipulate spaces of billions of designs in seconds to minutes for the kernels evaluated.

Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach

TL;DR

This work tackles the challenge of automatically selecting HLS pragmas to optimize kernel QoR by introducing NLP-DSE, a non-linear programming framework that targets affine, regular-loop programs. By building an analytical, latency-and-resource model compatible with the Merlin/Vitis toolchain and proving a latency lower bound, the approach enables fast pruning of vast design spaces and efficient pragma optimization. NLP-DSE consistently achieves equal or better QoR than AutoDSE and HARP across numerous benchmarks, often with orders of magnitude faster design-space exploration. The method demonstrates strong potential for practical FPGA development, offering interpretable performance estimates and scalable search, with future work guiding more extensive code transformations beyond pragma insertion. The practical impact lies in dramatically reducing design time while delivering high-quality hardware accelerators for AI, linear algebra, and data-processing kernels.

Abstract

High-Level Synthesis enables the rapid prototyping of hardware accelerators, by combining a high-level description of the functional behavior of a kernel with a set of micro-architecture optimizations as inputs. Such optimizations can be described by inserting pragmas e.g. pipelining and replication of units, or even higher level transformations for HLS such as automatic data caching using the AMD/Xilinx Merlin compiler. Selecting the best combination of pragmas, even within a restricted set, remains particularly challenging and the typical state-of-practice uses design-space exploration to navigate this space. But due to the highly irregular performance distribution of pragma configurations, typical DSE approaches are either extremely time consuming, or operating on a severely restricted search space. This work proposes a framework to automatically insert HLS pragmas in regular loop-based programs, supporting pipelining, unit replication, and data caching. We develop an analytical performance and resource model as a function of the input program properties and pragmas inserted, using non-linear constraints and objectives. We prove this model provides a lower bound on the actual performance after HLS. We then encode this model as a Non-Linear Program, by making the pragma configuration unknowns of the system, which is computed optimally by solving this NLP. This approach can also be used during DSE, to quickly prune points with a (possibly partial) pragma configuration, driven by lower bounds on achievable latency. We extensively evaluate our end-to-end, fully implemented system, showing it can effectively manipulate spaces of billions of designs in seconds to minutes for the kernels evaluated.
Paper Structure (60 sections, 15 theorems, 22 equations, 5 figures, 10 tables, 1 algorithm)

This paper contains 60 sections, 15 theorems, 22 equations, 5 figures, 10 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Pragma-based Optimizations for HLS
  4. DSE for Pragma Insertion
  5. AutoDSE
  6. HARP
  7. Limitations of General-Purpose DSE
  8. Exploration of the space
  9. Lack of full understanding of pragma impact
  10. Parallelism imbalance
  11. Limitations of filtering-based approaches
  12. Overview of NLP-DSE
  13. Modeling Programs and Their Pragmas
  14. Program Representation
  15. Non-Linear Formulation for Pragma Insertion
  16. ...and 45 more sections

Key Result

theorem 1

Given infinite resources, and assuming no operation nor memory movement can take less than one cycle to complete, the latency $LAT_{cp}^L \ge \#OG_{cp}^L$ is a lower bound on the minimal feasible latency to execute $L$.

Figures (5)

  • Figure 1: Comparison between the throughput (GF/s) and Design Space Exploration (DSE) time (min) of NLP-DSE and AutoDSE for large problem sizes in Polybench.
  • Figure 2: Comparison between the throughput (GF/s) and Design Space Exploration (DSE) time (min) of NLP-DSE and AutoDSE for medium problem sizes in Polybench.
  • Figure 3: Comparison between the throughput (GF/s) of NLP-DSE and HARP for small and medium problem sizes in Polybench.
  • Figure 4: Comparison of the Latency Between the Design Reported in the HLS Report and the Lower Bound Estimate Provided by the Nonlinear Problem for All Explored Designs, Specifically for Cases Where Pragmas Were Applied as Expected, with ID Rank Representing the Order of Designs Sorted by HLS Latency.
  • Figure 5: Representation of the throughput (GF/s) achieved for each design obtained at each stage of the NLP-DSE for the 2mm kernel.

Theorems & Definitions (21)

  • definition 1: Straight-line code
  • definition 2: Live-in set
  • definition 3: Live-out set
  • definition 4: Operation Graph
  • definition 5: Operation Graph critical path
  • theorem 1: Lower bound on latency of an Operation Graph
  • theorem 2: Latency Lower Bound under Operation Resource Constraints
  • corollary 1: Equivalence between fully unrolled and straight-line code
  • theorem 3: Minimal latency of a fully unrolled loop nest
  • theorem 4: Minimal latency of a partially unrolled loop with factor UF
  • ...and 11 more