Efficient and Scalable Architectures for Multi-Level Superconducting Qubit Readout

TL;DR

This work tackles leakage errors in multi-level superconducting qubits by developing a scalable three-level readout that integrates matched filters with a lightweight neural network. The method achieves a 60x reduction in FPGA LUT usage, a 20% reduction in readout time, and a 100x smaller neural network, with a 6.6% relative improvement in readout accuracy over the baseline. It uses per-qubit matched filters (QMF, RMF, EMF) and a small NN, plus leakage-cluster detection without explicit calibration via mean-trace clustering to enable fast leakage mitigation. Evaluated on a five-qubit dataset, the approach delivers hardware-friendly FPGA deployment with lower latency and improved leakage-speculation performance, strengthening QEC reliability and advancing scalable fault-tolerant quantum computing.

Abstract

Realizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by $60\times$ compared to the baseline while reducing readout time by 20\%, enabling faster leakage detection. By employing matched filters to detect relaxation and excitation error patterns and integrating a modular lightweight neural network to correct crosstalk errors, the protocol significantly reduces hardware complexity, achieving a $100\times$ reduction in neural network size. Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a 6.6\% relative improvement in readout accuracy over the baseline. This innovation enables faster leakage mitigation, enhances QEC reliability, and accelerates the path toward fault-tolerant quantum computing.

Figures (5)

• Figure 1: (a) Computational and Leakage levels in a qubit. (b) Overview of readout pipeline. (c) Comparison of readout classification inaccuracy over all five qubits used in Ref. Blienhard. (d) LUT utilization of using herqules HERCULES, Feedforward Neural Network (FNN) design Blienhard, and our proposed method.
• Figure 2: Design overview of FNN Blienhard(top) and herqulesHERCULES(bottom)
• Figure 3: Averaged IQ data points for (a) two-level readout and (b) after detecting instances of natural leakage using spectral clustering. Mean traces of the clusters of (c) qubit states and (d) excitation error instances
• Figure 4: Overview of our Design. (a) The qubit traces are processed with matched filter envelopes by dot-product to output a single value for each envelope. (b) The data from all the qubits are merged to send the data as the input to a Feed-Forward Neural Network (FNN). (c) Our design of FNN to output qudit states.
• Figure 5: (a) Comparison of FPGA resource utilization (b)Variation of mean accuracy with readout duration in nanoseconds