A Second-Order Audio VCO-ADC with 103-dB-A Dynamic Range and Binary-Weighted Internal Architecture

TL;DR

This work tackles the limited noise-shaping order of conventional VCO-ADCs by introducing a True-VCO-ADC that uses binary-weighted intermediate values and Gray-encoded ring oscillators to achieve high dynamic range without analog feedback DACs. The architecture rearranges a conventional second-order sigma-delta loop into a modulo-arithmetic, mostly-digital implementation, where state variables are represented in binary/Gray form and feedback is performed digitally, yielding second-order noise shaping with robust performance to process, voltage, and temperature variations. The authors derive a linear model with $NTF(z)=\frac{(1-z^{-1})^2}{1-(1-k_{DCO}/f_s)z^{-1}}$ and $STF=\frac{k_{vco}}{f_s}\cdot sinc(f)^2$, and demonstrate a 130 nm chip achieving 103 dB dynamic range and 76.5 dB-A peak SNDR at 250 µW in 0.095 mm$^2$, suitable for direct MEMS microphone interfacing. This approach significantly reduces circuit area growth with bit-depth, enabling high-DR audio converters in compact, low-power MEMS-enabled systems.

Abstract

One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True-VCO architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True-VCO architectures represent state variables either with a thermometer code or with a single-bit. Thermometer encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force thermometer-encoded state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we show experimentally a second-order audio VCO-based ADC which uses ring oscillators as integrators but employs Gray and binary encoding for state variables. As a consequence, the complexity and area of the True-VCO architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The implemented chip shows a dynamic range of 103~dB achieving a peak SNDR of 76.5 dB-A with a power of 250 $μ$W occupying 0.095 $\text{mm}^2$ in 130 nm CMOS.

Figures (15)

• Figure 1: (a) Loop integrator approach, analog feedback DAC, (b) Up-down counter, (c) proposed binary weighted architecture.
• Figure 2: Different ways of building a second-order CTSD modulator, (a) typical CTSDM, (b) splitting input integrator, (c) substituting inner loop with a first-order VCO-ADC, (d) nested first-order CTSDM.
• Figure 3: Average of 32 FFT from system level simulations of Fig. \ref{['fig:evolution_DS_to_Proposed']}(a) and Fig. \ref{['fig:evolution_DS_to_Proposed']}(b).
• Figure 4: Operation of the subtraction element SB with modular arithmetic.
• Figure 5: Extension to higher order modulators.