Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

A Compact Delay Model for OTS Devices

M. M. Al Chawa, R. Tetzlaff, D. Bedau, J. W. Reiner, D. A. Stewart, M. K. Grobis

TL;DR

This paper addresses the need for efficient, SPICE-friendly models of Ovonic Threshold Switch devices whose I–V behavior features current-controlled negative differential resistance and abrupt threshold switching. It introduces a compact delay-based internal state variable integrated into a five-junction OTS equivalent circuit to achieve a SPICE-compatible representation. A closed-form i(v, v_R) expression is derived and coupled with an off-state leakage model, with parameters fitted to Se-based OTS devices from Western Digital Research. The results show good agreement with experimental data, including snapback behavior, providing a practical tool for circuit designers of OTS-based selectors, switches, and neuromorphic applications.

Abstract

This paper presents a novel compact delay model of Ovonic Threshold Switch (OTS) devices that works efficiently for circuit simulations. The internal state variable of the two terminal devices is estimated using a delay system that uses a few electrical components related to a suggested equivalent circuit of the device. Finally, we tested the proposed model against measured data from devices fabricated by Western Digital Research.

A Compact Delay Model for OTS Devices

TL;DR

This paper addresses the need for efficient, SPICE-friendly models of Ovonic Threshold Switch devices whose I–V behavior features current-controlled negative differential resistance and abrupt threshold switching. It introduces a compact delay-based internal state variable integrated into a five-junction OTS equivalent circuit to achieve a SPICE-compatible representation. A closed-form i(v, v_R) expression is derived and coupled with an off-state leakage model, with parameters fitted to Se-based OTS devices from Western Digital Research. The results show good agreement with experimental data, including snapback behavior, providing a practical tool for circuit designers of OTS-based selectors, switches, and neuromorphic applications.

Abstract

This paper presents a novel compact delay model of Ovonic Threshold Switch (OTS) devices that works efficiently for circuit simulations. The internal state variable of the two terminal devices is estimated using a delay system that uses a few electrical components related to a suggested equivalent circuit of the device. Finally, we tested the proposed model against measured data from devices fabricated by Western Digital Research.
Paper Structure (6 sections, 14 equations, 4 figures, 1 table)

This paper contains 6 sections, 14 equations, 4 figures, 1 table.

Table of Contents

  1. Introduction
  2. Model Description and Implementation
  3. OTS Equivalent Circuit
  4. Internal State Variable
  5. Model Implementation
  6. Conclusion

Figures (4)

  • Figure 1: OTS cell equivalent circuit.
  • Figure 2: The Delay model extracted from $J_2$ in Fig. \ref{['fig:newcircuit']} to obtain the internal state variable. (a) The proposed circuit related to the $J_2$ : $C_{2}=10nF$, $R_b=1M\Omega$ and $I_{state}=1\mu A$; (b) The values of the internal state variable (voltage drop across the circuit in Fig. \ref{['fig:a1']}) vs. time (a.u.).
  • Figure 3: (a) Derivative of the internal voltage drop $v_R$ across the $J_2$ ($K=0.7$); (b) Capacitive current through $J_2$ ($v \approx v_R$) in \ref{['eq:QC']} considering a linear capacitor approximation, ($C \approx 10nF$).
  • Figure 4: $i\text{--}v$ curve, red dots are (normalized) experimental data (symbols) and modeled using \ref{['eq:final model']} (blue line) for OTS devices. The devices and experimental measurements obtained by Western Digital Research10225437.