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LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust

Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu

TL;DR

The paper addresses the security and trust challenges of integrating LxMs into chip design, proposing a comprehensive survey of how LLMs, LMMs, and LCMs are applied to EDA and hardware security. It classifies existing work into two main domains—LLMs for EDA and LLMs for hardware security—and analyzes attack and defense perspectives, including HT insertion, IP leakage, SCA countermeasures, and HDL bug repair. Key contributions include a detailed taxonomy, critical assessments of Verilog RTL generation, HLS and design-automation workflows, and techniques for generating security properties and assertions, as well as outlining important future directions for representation alignment, optimization, and secure LxM deployment. The discussion highlights both the potential of LxMs to accelerate chip design and the pressing need to address privacy, security, and trust concerns before widespread adoption in industry. Overall, the work provides a roadmap for researchers and practitioners and points to the LLM4IC hub as a resource for ongoing development in this rapidly evolving area.

Abstract

Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous potential, the community must also carefully consider the related security risks and the need for building trust into using LxMs for chip design. First, we review the recent surge of using LxMs for chip design in general. We cover state-of-the-art works for the automation of hardware description language code generation and for scripting and guidance of essential but cumbersome tasks for electronic design automation tools, e.g., design-space exploration, tuning, or designer training. Second, we raise and provide initial answers to novel research questions on critical issues for security and trustworthiness of LxM-powered chip design from both the attack and defense perspectives.

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust

TL;DR

The paper addresses the security and trust challenges of integrating LxMs into chip design, proposing a comprehensive survey of how LLMs, LMMs, and LCMs are applied to EDA and hardware security. It classifies existing work into two main domains—LLMs for EDA and LLMs for hardware security—and analyzes attack and defense perspectives, including HT insertion, IP leakage, SCA countermeasures, and HDL bug repair. Key contributions include a detailed taxonomy, critical assessments of Verilog RTL generation, HLS and design-automation workflows, and techniques for generating security properties and assertions, as well as outlining important future directions for representation alignment, optimization, and secure LxM deployment. The discussion highlights both the potential of LxMs to accelerate chip design and the pressing need to address privacy, security, and trust concerns before widespread adoption in industry. Overall, the work provides a roadmap for researchers and practitioners and points to the LLM4IC hub as a resource for ongoing development in this rapidly evolving area.

Abstract

Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous potential, the community must also carefully consider the related security risks and the need for building trust into using LxMs for chip design. First, we review the recent surge of using LxMs for chip design in general. We cover state-of-the-art works for the automation of hardware description language code generation and for scripting and guidance of essential but cumbersome tasks for electronic design automation tools, e.g., design-space exploration, tuning, or designer training. Second, we raise and provide initial answers to novel research questions on critical issues for security and trustworthiness of LxM-powered chip design from both the attack and defense perspectives.
Paper Structure (32 sections, 1 figure, 1 table)

This paper contains 32 sections, 1 figure, 1 table.

Table of Contents

  1. Introduction
  2. Background
  3. Large Language Models
  4. Learning Paradigms
  5. Interacting Mechanisms
  6. LMM/LCM
  7. Electronic Design Automation
  8. Hardware Security
  9. Hardware Trojans (HTs)
  10. IP Piracy and Chip Overbuilding
  11. Side-Channel Attacks (SCA)
  12. Further Considerations
  13. Proposed Taxonomy
  14. LLMs for Electronic Design Automation
  15. Verilog RTL Generation
  16. ...and 17 more sections

Figures (1)

  • Figure 1: Overview of selected LLM applications for EDA in general (blue) and for hardware security in particular (purple).