Investigating impact of bit-flip errors in control electronics on quantum computation

TL;DR

The paper addresses how bit-flip faults in FPGA BRAM storing quantum pulse envelopes degrade quantum gate fidelity. It employs a systematic single-bit flip sensitivity analysis on amplitude (I and Q) and phase data across IBM fake backends, quantified by the Total Variation Distance ($TVD$), and demonstrates that exponent and early mantissa bits are the primary sources of disruption. A $3$-bit repetition code is proposed and shown to reduce $TVD$ increases from up to ~200% to below ~7% for targeted bits, with some overhead-related residual error; SECDED is discussed as an alternative with parity overhead. The findings inform hardware-level fault-tolerance design for quantum control, highlighting which memory bits to protect and the trade-offs between error resilience and memory resources.

Abstract

In this paper, we investigate the impact of bit flip errors in FPGA memories in control electronics on quantum computing systems. FPGA memories are integral in storing the amplitude and phase information pulse envelopes, which are essential for generating quantum gate pulses. However, these memories can incur faults due to physical and environmental stressors such as electromagnetic interference, power fluctuations, and temperature variations and adversarial fault injections, potentially leading to errors in quantum gate operations. To understand how these faults affect quantum computations, we conducted a series of experiments to introduce bit flips into the amplitude (both real and imaginary components) and phase values of quantum pulses using IBM's simulated quantum environments, FakeValencia, FakeManila, and FakeLima. Our findings reveal that bit flips in the exponent and initial mantissa bits of the real amplitude cause substantial deviations in quantum gate operations, with TVD increases as high as ~200%. Interestingly, the remaining bits exhibited natural tolerance to errors. We proposed a 3-bit repetition error correction code, which effectively reduced the TVD increases to below 40% without incurring any memory overhead. Due to reuse of less significant bits for error correction, the proposed approach introduces maximum of 5-7% extra TVD in nominal cases. However, this can be avoided by sacrificing memory area for implementing the repetition code.

Figures (9)

• Figure 1: Qubit control system hardware and instruction Cycle in quantum computing using FPGA: Key components include the master oscillator (MO), clock (CLK), local oscillator (LO), field-programmable gate array (FPGA), digital-to-analog converter (DAC), analog-to-digital converter (ADC), upconverter (UP) and downconverter (DN). The diagram also depicts the instruction cycle, where the FPGA memory retrieves and processes amplitude and phase details for each quantum gate, converting these details via a modulator into precise RF pulses directed at the quantum processor unit (QPU), enabling effective quantum operations.
• Figure 2: Pulse shape impact from bit flip in Hadamard Gate. The bottom graph shows the original pulse amplitude for IBM's FakeValencia Hadamard Gate, and the top graph illustrates the drastic reduction in amplitude caused by a third-bit flip in FPGA memory.
• Figure 3: TVD increase from bit flips in the real part of amplitude for (a) X and, (b) H gates across three simulated backends: FakeValencia, FakeManila, and FakeLima demonstrating consistent sensitivity trend across backends.
• Figure 4: TVD increase from bit flips in the real part of amplitude for various quantum gates simulated in FakeValencia backend.
• Figure 5: TVD increase from bit flips in the imaginary part of amplitude for various quantum gates simulated in FakeValencia backend.