PARSAC: Fast, Human-quality Floorplanning for Modern SoCs with Complex Design Constraints

TL;DR

This work tackles modern SoC floorplanning under hard placement constraints by introducing Constraints-Aware Simulated Annealing (CA-SA), which uses constraint-fixing moves and a B*-tree with anchored blocks to guarantee feasibility. Building on CA-SA, the authors develop PARSAC, a massively parallel framework that scales across CPU cores and machines to rapidly generate Pareto fronts balancing HPWL and area. Empirical results on legacy and constraint-rich benchmarks show that CA-SA consistently outperforms vanilla SA and that PARSAC delivers legal, high-quality floorplans with substantial improvements in constraint satisfaction and solution diversity. The approach offers a practical, reproducible open-source tool for industry-relevant floorplanning with complex design constraints.

Abstract

The floorplanning of Systems-on-a-Chip (SoCs) and of chip sub-systems is a crucial step in the physical design flow as it determines the optimal shapes and locations of the blocks that make up the system. Simulated Annealing (SA) has been the method of choice for tackling classical floorplanning problems where the objective is to minimize wire-length and the total placement area. The goal in industry-relevant floorplanning problems, however, is not only to minimize area and wire-length, but to do that while respecting hard placement constraints that specify the general area and/or the specific locations for the placement of some blocks. We show that simply incorporating these constraints into the SA objective function leads to sub-optimal, and often illegal, solutions. We propose the Constraints-Aware Simulated Annealing (CA-SA) method and show that it strongly outperforms vanilla SA in floorplanning problems with hard placement constraints. We developed a new floorplanning tool on top of CA-SA: PARSAC (Parallel Simulated Annealing with Constraints). PARSAC is an efficient, easy-to-use, and massively parallel floorplanner. Unlike current SA-based or learning-based floorplanning tools that cannot effectively incorporate hard placement-constraints, PARSAC can quickly construct the Pareto-optimal legal solutions front for constrained floorplanning problems. PARSAC also outperforms traditional SA on legacy floorplanning benchmarks. PARSAC is available as an open-source repository for researchers to replicate and build on our result.

Figures (7)

• Figure 1: The SoC and sub-system floorplanning task includes hierarchy-level partition shaping, partition placement and pin placement on the partition. Our work is applicable to both SoC and sub-system level partition placement and partition shaping.
• Figure 2: An example of a compacted floorplan (left) and the corresponding B*-tree (right) representation. Given a compact layout, a tree representation can be obtained by traversing the blocks, starting from the lower-left module $b1$. Likewise, given a B*Tree, layout can be obtained by a DFS traversal, starting from the root node $b1$.
• Figure 3: An example of a hard constraints local minimum. There is one violating block (shown with a red outline) that should be placed on the bottom boundary. The bottom boundary is already filled with constrained blocks. Moving the violating block and placing it to the right of one of the bottom-boundary blocks will increase the width of the bottom row and move the right edge of the floorplan. This will result in constraint violations at all the constrained right edge blocks (green blocks) because they will no longer be at the right edge of the floorplan.
• Figure 4: PARSAC architecture.
• Figure 5: Histogram of boundary constraints violations for CA-SA and classical SA for the constrained n100, n200, and n300 problems. The statistics for each problem were collected from 336 trials.