Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?

TL;DR

The paper evaluates whether a fully open-source EDA flow can scale to multi-million-gate Linux-capable RV64GC SoCs by incrementally improving the Yosys+OpenROAD toolchain. It introduces three synthesis enhancements—Part-Select Synthesis, an ABC script overhaul with lazy-synthesis, and a Library of Arithmetic Units—and a routability-aware Place & Route flow, culminating in Basilisk, taped out in IHP's open 130nm process at $77$ MHz with a 1.1M-gate core. Quantitative gains include a $2.3\times$ speedup over the Iguana baseline, a $1.6\times$ area reduction, a $2.5\times$ reduction in synthesis time, and a $2.9\times$ RAM reduction, with a timing-optimized variant reaching $97$ MHz and Basilisk achieving a zero-violation tapeout and $55\%$ core utilization. The work demonstrates a concrete, open-path workflow toward high-end SoC tapeouts and provides benchmarks (e.g., Basilisk and LAU) for community-driven tool development, while outlining remaining gaps relative to commercial flows and calling for timing-driven integration and standardized formats.

Abstract

Designing complex, multi-million-gate application-specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-on-chip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP's open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3x improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6x. Furthermore, tool runtime was reduced by 2.5x, and peak RAM usage decreased by 2.9x. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.

Figures (6)

• Figure 1: Preprocessing, synthesis and flow used for Iguana and Basilisk
• Figure 2: Step-by-step preprocessing and synthesis of a part select operation
• Figure 3: A example for a simple example network (left). Three input cuts are generated from the network and the three input records (right) are probed. The best implementation is taken and inserted into the graph.
• Figure 4: Yosys elaborated and synthesized datapath (left, middle) and our optimized datapath (right) with unit delays.
• Figure 5: Layout files produced by running the original Iguana flow (a) and of Basilisk (b).