Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC

TL;DR

Basilisk presents an optimized, tapeout-ready open-source ASIC flow that extends the Iguana framework by refining synthesis and physical design using open tools (Yosys, OpenROAD, ABC) on a 130 nm IHP process. Through targeted improvements to SystemVerilog handling, part-select encoding, and MAC/CSA optimizations, along with power-grid redesign and routability-tuned placement, Basilisk achieves a 2.3× increase in clock frequency and higher core utilization with fewer post-routing violations. The work demonstrates that competitive ASIC performance is attainable with fully open-source EDA toolchains and contributes optimized flow scripts and practical benchmarks for the community. The authors also plan to tape out Basilisk and release hardware-ready designs to foster ongoing collaboration in open-source hardware development.

Abstract

We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (SoC). We present enhancements to synthesis tools and logic optimization scripts improving quality of results (QoR), as well as an optimized physical design with an improved power grid and cell placement integration enabling a higher core utilization. The tapeout-ready version of Basilisk implemented in IHP's open 130 nm technology achieves an operation frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3x improvement compared to the baseline open-source EDA design flow presented in Iguana, and a higher 55 % core utilization compared to 50 % in the baseline design. Through collaboration with EDA tool developers and domain experts, Basilisk exemplifies a synergistic effort towards competitive open-source electronic design automation (EDA) tools for research and industry applications.

Figures (1)

• Figure 1: Amoeba view; Iguana (left) and Basilisk(right).