Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT

TL;DR

The paper addresses the time-consuming process of hardware design for neuromorphic RSNNs by prompting OpenAI's ChatGPT-4 to generate Verilog RTL and test benches for a $3$-layer RSNN with $3$ neurons per layer ($27$ weights). A modular, bottom-up workflow yields submodules and a top-level integration, validated through FPGA prototyping on Spartan-7 and an open-source SkyWater 130 nm ASIC flow leading to Tiny Tapeout 6. The RSNN and its LIF neurons are demonstrated across three ML benchmarks—XOR, IRIS, MNIST—with accuracies exceeding 96% in most cases, and the work includes comprehensive open-source artifacts (code, tests, transcripts). This illustrates a reproducible AI-assisted hardware design pipeline that leverages open-source EDA tools to rapidly prototype neuromorphic accelerators. The results suggest practical potential for LTspice-like design iterations accelerated by LLMs, enabling broader exploration of hardware-software co-design for spiking networks.

Abstract

This paper investigates the use of Large Language Models (LLMs) and natural language prompts to generate hardware description code, namely Verilog. Building on our prior work, we employ OpenAI's ChatGPT4 and natural language prompts to synthesize an RTL Verilog module of a programmable recurrent spiking neural network, while also generating test benches to assess the system's correctness. The resultant design was validated in three simple machine learning tasks, the exclusive OR, the IRIS flower classification and the MNIST hand-written digit classification. Furthermore, the design was validated on a Field-Programmable Gate Array (FPGA) and subsequently synthesized in the SkyWater 130 nm technology by using an open-source electronic design automation flow. The design was submitted to Efabless Tiny Tapeout 6.

Figures (5)

• Figure 1: Schema of the desired Recurrent Spiking Neural Network, consisting of 3 fully connected layers, each layer having 3 recurrent spiking neurons.
• Figure 2: Block Diagram describing the pipeline used for our proposed Sequential MNIST model.
• Figure 3: Timing Post-Implementation Simulation of the RSNN hardware design generated by ChatGPT on Spartan 7 FPGA. The system operates in two functional modes: startup mode, where load_params goes high enabling the loading of all network parameters into memory, and running mode, where the spikeIN_reg_enable signal enables the storage of input spikes and their processing, allowing the system to generate output spikes.
• Figure 4: Timing Post-Implementation Simulation of the RSNN hardware design generated by ChatGPT on Spartan 7 FPGA. Zoomed-in view of the startup mode, where the load_params signal is asserted high, enabling the loading of all network parameters into memory. This phase is crucial for initializing the network with the correct parameters before transitioning to the running mode.
• Figure 5: 2D Visualization of the GDSII file of the RSNN hardware design generated by ChatGPT in SkyWater 130 nm technology.