Active Dendrites Enable Efficient Continual Learning in Time-To-First-Spike Neural Networks
Lorenzo Pes, Rick Luiken, Federico Corradi, Charlotte Frenkel
TL;DR
The paper tackles catastrophic forgetting in sequential learning by integrating time-to-first-spike TTFS encoding with active dendrites in spiking neural networks. The approach modulates spike-time timing via dendritic delays and selects per-task subnetworks, enabling continual learning with reduced interference. Key contributions include the dendritic delay modulation mechanism, a dual-parameter learning framework (W and u), and a hardware architecture with per-task dendritic timing implemented on FPGA, achieving 80% accuracy at 37.3 ms on edge hardware. The results show competitive Split-MNIST performance and practical edge deployment feasibility, highlighting the potential for energy-efficient, continual-learning neuromorphic systems. The work advances TTFS-based SNNs toward scalable, real-time edge applications by combining biologically inspired dendritic processing with hardware-ready architectures.
Abstract
While the human brain efficiently adapts to new tasks from a continuous stream of information, neural network models struggle to learn from sequential information without catastrophically forgetting previously learned tasks. This limitation presents a significant hurdle in deploying edge devices in real-world scenarios where information is presented in an inherently sequential manner. Active dendrites of pyramidal neurons play an important role in the brain ability to learn new tasks incrementally. By exploiting key properties of time-to-first-spike encoding and leveraging its high sparsity, we present a novel spiking neural network model enhanced with active dendrites. Our model can efficiently mitigate catastrophic forgetting in temporally-encoded SNNs, which we demonstrate with an end-of-training accuracy across tasks of 88.3% on the test set using the Split MNIST dataset. Furthermore, we provide a novel digital hardware architecture that paves the way for real-world deployment in edge devices. Using a Xilinx Zynq-7020 SoC FPGA, we demonstrate a 100-% match with our quantized software model, achieving an average inference time of 37.3 ms and an 80.0% accuracy.
