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Active Dendrites Enable Efficient Continual Learning in Time-To-First-Spike Neural Networks

Lorenzo Pes, Rick Luiken, Federico Corradi, Charlotte Frenkel

TL;DR

The paper tackles catastrophic forgetting in sequential learning by integrating time-to-first-spike TTFS encoding with active dendrites in spiking neural networks. The approach modulates spike-time timing via dendritic delays and selects per-task subnetworks, enabling continual learning with reduced interference. Key contributions include the dendritic delay modulation mechanism, a dual-parameter learning framework (W and u), and a hardware architecture with per-task dendritic timing implemented on FPGA, achieving 80% accuracy at 37.3 ms on edge hardware. The results show competitive Split-MNIST performance and practical edge deployment feasibility, highlighting the potential for energy-efficient, continual-learning neuromorphic systems. The work advances TTFS-based SNNs toward scalable, real-time edge applications by combining biologically inspired dendritic processing with hardware-ready architectures.

Abstract

While the human brain efficiently adapts to new tasks from a continuous stream of information, neural network models struggle to learn from sequential information without catastrophically forgetting previously learned tasks. This limitation presents a significant hurdle in deploying edge devices in real-world scenarios where information is presented in an inherently sequential manner. Active dendrites of pyramidal neurons play an important role in the brain ability to learn new tasks incrementally. By exploiting key properties of time-to-first-spike encoding and leveraging its high sparsity, we present a novel spiking neural network model enhanced with active dendrites. Our model can efficiently mitigate catastrophic forgetting in temporally-encoded SNNs, which we demonstrate with an end-of-training accuracy across tasks of 88.3% on the test set using the Split MNIST dataset. Furthermore, we provide a novel digital hardware architecture that paves the way for real-world deployment in edge devices. Using a Xilinx Zynq-7020 SoC FPGA, we demonstrate a 100-% match with our quantized software model, achieving an average inference time of 37.3 ms and an 80.0% accuracy.

Active Dendrites Enable Efficient Continual Learning in Time-To-First-Spike Neural Networks

TL;DR

The paper tackles catastrophic forgetting in sequential learning by integrating time-to-first-spike TTFS encoding with active dendrites in spiking neural networks. The approach modulates spike-time timing via dendritic delays and selects per-task subnetworks, enabling continual learning with reduced interference. Key contributions include the dendritic delay modulation mechanism, a dual-parameter learning framework (W and u), and a hardware architecture with per-task dendritic timing implemented on FPGA, achieving 80% accuracy at 37.3 ms on edge hardware. The results show competitive Split-MNIST performance and practical edge deployment feasibility, highlighting the potential for energy-efficient, continual-learning neuromorphic systems. The work advances TTFS-based SNNs toward scalable, real-time edge applications by combining biologically inspired dendritic processing with hardware-ready architectures.

Abstract

While the human brain efficiently adapts to new tasks from a continuous stream of information, neural network models struggle to learn from sequential information without catastrophically forgetting previously learned tasks. This limitation presents a significant hurdle in deploying edge devices in real-world scenarios where information is presented in an inherently sequential manner. Active dendrites of pyramidal neurons play an important role in the brain ability to learn new tasks incrementally. By exploiting key properties of time-to-first-spike encoding and leveraging its high sparsity, we present a novel spiking neural network model enhanced with active dendrites. Our model can efficiently mitigate catastrophic forgetting in temporally-encoded SNNs, which we demonstrate with an end-of-training accuracy across tasks of 88.3% on the test set using the Split MNIST dataset. Furthermore, we provide a novel digital hardware architecture that paves the way for real-world deployment in edge devices. Using a Xilinx Zynq-7020 SoC FPGA, we demonstrate a 100-% match with our quantized software model, achieving an average inference time of 37.3 ms and an 80.0% accuracy.
Paper Structure (11 sections, 10 equations, 4 figures)

This paper contains 11 sections, 10 equations, 4 figures.

Figures (4)

  • Figure 1: Human versus conventional ML learning. a The human brain can learn new tasks in a sequential order without forgetting previous ones. b Training ML models in a sequential order leads to catastrophic forgetting. c Interleaving samples when training ML models avoids catastrophic forgetting.
  • Figure 2: Neuron model and network architecture.a Bottom: linear integration of synaptic strength $W_{ij}$ following a pre-synaptic spike at $t_i$. Top: dendritic modulation of the spike time delay. b Illustration of a pyramidal neuron. c Selection of different sub-networks for different tasks based on the activity of dendritic segments. Dead neurons are used to efficiently implement a gating mechanism, with outgoing synaptic connections shown in gray (connections from active neurons are shown in blue). d Proposed neuron model and dendritic activation function.
  • Figure 3: Digital Hardware Architecture. a Architecture of a layer containing $J$ parallel neuron processing units (NPUs). b Block diagram of an NPU implementing the dynamics of the proposed neuron model. The synaptic register accumulates the synaptic strength (i.e., $W$) received at each timestep. The membrane register stores the membrane voltage of the neuron. It integrates the value stored in the synaptic register at the end of each timestep. The down counter is loaded with the dendritic delay of the current task. Following a threshold crossing event, it starts decrementing at each timestep. When its value reaches zero, it raises the SPIKED flag.
  • Figure 4: Split-MNIST setup and results.a Example of three distinct tasks, each aiming to differentiate between two digits. b Test accuracy for each task over training time for the model without active dendrites (top) and with active dendrites (bottom). Note that a new task is introduced every 5 training epochs. c Average accuracy across tasks at the end of training for three experiments.