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Time Reversal for Near-Field Communications on Multi-chip Wireless Networks

Fátima Rodríguez-Galán, Ama Bandara, Elana Pereira de Santana, Peter Haring Bolívar, Eduard Alarcón, Sergi Abadal

TL;DR

Evidence is offered, via full-wave simulations at 140 GHz, that TR can increase the symbol rate by an order of magnitude, and enable multiple concurrent high-speed links at the chip scale, and allow the deployment of multiple concurrent links toward achieving aggregate speeds in excess of 100 Gb/s.

Abstract

Wireless Network-on-Chip (WNoC) has been proposed as a low-latency, versatile, and broadcast-capable complement to current interconnects in the quest for satisfying the ever-increasing communications needs of modern computing systems. However, to realize the promise of WNoC, multiple wireless links operating at several tens of Gb/s need to be created within a computing package. Unfortunately, the highly integrated and enclosed nature of such computing packages incurs significant Co-Channel Interference (CCI) and Inter-Symbol Interference (ISI), not only preventing the deployment of multiple spatial channels, but also severely limiting the symbol rate of each individual channel. In this work, Time Reversal (TR) is proposed as a means to compensate the channel impairments and enable multiple concurrent high-speed links at the chip scale. We offer evidence, via full-wave simulations at 140 GHz, that TR can increase the symbol rate by an order of magnitude and allow the deployment of multiple concurrent links towards achieving aggregate speeds in excess of 100 Gb/s. Finally, the challenges relative to the realization of TR at the chip scale are analyzed from the implementation, protocol support, and architectural perspectives.

Time Reversal for Near-Field Communications on Multi-chip Wireless Networks

TL;DR

Evidence is offered, via full-wave simulations at 140 GHz, that TR can increase the symbol rate by an order of magnitude, and enable multiple concurrent high-speed links at the chip scale, and allow the deployment of multiple concurrent links toward achieving aggregate speeds in excess of 100 Gb/s.

Abstract

Wireless Network-on-Chip (WNoC) has been proposed as a low-latency, versatile, and broadcast-capable complement to current interconnects in the quest for satisfying the ever-increasing communications needs of modern computing systems. However, to realize the promise of WNoC, multiple wireless links operating at several tens of Gb/s need to be created within a computing package. Unfortunately, the highly integrated and enclosed nature of such computing packages incurs significant Co-Channel Interference (CCI) and Inter-Symbol Interference (ISI), not only preventing the deployment of multiple spatial channels, but also severely limiting the symbol rate of each individual channel. In this work, Time Reversal (TR) is proposed as a means to compensate the channel impairments and enable multiple concurrent high-speed links at the chip scale. We offer evidence, via full-wave simulations at 140 GHz, that TR can increase the symbol rate by an order of magnitude and allow the deployment of multiple concurrent links towards achieving aggregate speeds in excess of 100 Gb/s. Finally, the challenges relative to the realization of TR at the chip scale are analyzed from the implementation, protocol support, and architectural perspectives.
Paper Structure (7 sections, 4 figures, 1 table)

This paper contains 7 sections, 4 figures, 1 table.

Table of Contents

  1. Introduction
  2. Time Reversal for on-Chip Communications
  3. ISI Mitigation: Single-Link Analysis
  4. CCI Mitigation: Towards Multiple-Input-Multiple-Output with TR
  5. Challenges
  6. Conclusion
  7. Section

Figures (4)

  • Figure 1: Interposer package with four chiplets and multiple wireless chips-scale links. With time reversal, the transmitted signal is spatiotemporally focused at the intended receiver, achieving high power with a short response. At non-intended receivers, the co-channel interference (CCI) level is diminished.
  • Figure 2: Single-link analysis of time reversal at 140 GHz in an interposer package. Bit error rate is plotted as a function of data rate of ASK modulation with and without time reversal for different links, assuming a transmission power of 10 dBm. For comparison, we also plot OFDM (32 subcarriers) and matched filter applied to one of the links.
  • Figure 3: Multi-link analysis of time reversal at 140 GHz considering nodes $A$ and $C$ transmitting concurrently, node $A$ sending different streams to receivers $B$ and $E$ simultaneously, and both at the same time. (a) Signal-to-Interference-Plus-Noise Ratio (SINR) of the multiple configurations. (b) Bit error rate as a function of aggregated data rate of ASK streams assuming a transmission power of 10 dBm per node.
  • Figure 4: Maximum aggregated data rates achieved with BER$<$10-3 for phase-modulated streams of increasing modulation order, with and without time reversal, assuming a transmission power of 10 dBm per node.