ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection

TL;DR

ICMarks tackles IP protection in modern IC physical design by introducing a two-level watermarking framework that operates during placement. It combines Global Watermarking to designate a robust watermarked region with Detailed Watermarking that encodes signatures via controlled cell moves, all while preserving wirelength and timing. Extensive benchmarks show ICMarks achieves high watermark extraction, substantial capacity (well over 200 bits in GW+DW modes), and strong resilience to both removal and forging attacks, with modest overhead and without harming routability. This region- and position-aware approach enhances practical IP protection across the IC supply chain, making ownership verification reliable even under sophisticated adversarial conditions.

Abstract

Physical design watermarking on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products. This paper presents ICMarks, a quality-preserving and robust watermarking framework for modern IC physical design. ICMarks embeds unique watermark signatures during the physical design's placement stage, thereby authenticating the IC layout ownership. ICMarks's novelty lies in (i) strategically identifying a region of cells to watermark with minimal impact on the layout performance and (ii) a two-level watermarking framework for augmented robustness toward potential removal and forging attacks. Extensive evaluations on benchmarks of different design objectives and sizes validate that ICMarks incurs no wirelength and timing metrics degradation, while successfully proving ownership. Furthermore, we demonstrate ICMarks is robust against two major watermarking attack categories, namely, watermark removal and forging attacks; even if the adversaries have prior knowledge of the watermarking schemes, the signatures cannot be removed without significantly undermining the layout quality.

Figures (11)

• Figure 1: The VLSI physical design process. It generates the IC layout from a design RTL through synthesis, placement, and routing stages.
• Figure 2: IC layout watermark scenario in the supply chain. The design company watermarks the IC layout before manufacturing and testing.
• Figure 3: Global watermarking pipeline with stride = sliding window size. The blue cells are the standard cells, the red cells are the macros, and the green cells are wm cells in GW.
• Figure 4: Detailed watermarking pipeline with Candidate cells from which Watermarked cells are selected.
• Figure 5: ICMarks framework. ICMarks first applies global watermarking during its global placement and then applies detailed watermarking on top of the watermarked region before the detailed placement. The green cells are the wm cells in GW stage and orange cells are the wm cells in DW stage.