Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout

TL;DR

The work tackles the challenge of incorporating fast, low-power, reconfigurable processing at the detector front-end to enable at-source ML in collider readout, where data rates reach hundreds of terabytes per second and latencies are on the order of nanoseconds. It uses the FABulous open-source framework to design embedded FPGAs (eFPGAs) in 130 nm and 28 nm CMOS, integrating them into ASICs with SUGOI control, AXI-Lite interfaces, and, at 28 nm, PGPv4-based AXI streams. A 130 nm proof-of-concept demonstrated basic programmability and power characterization, while the 28 nm version achieved a compact footprint with 448 LUTs, a successful AXI-stream loopback, and a 28 nm proof-of-concept ML application using a single-tree boosted decision tree (BDT) on a simulated smart-pixel dataset, delivering 100% hardware-vs-software accuracy and sub-25 ns runtime. The results establish the feasibility of eFPGAs for at-source readout in collider detectors and point to future work on larger, radiation-tolerant fabrics (e.g., TMR-enabled FABulous) and more capable ML implementations to meet the demands of next-generation high-energy physics experiments.

Abstract

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed.

Figures (12)

• Figure 1: Screenshot of the 130nm eFPGA tile configuration file.
• Figure 2: Block diagram of the 130nm CMOS ASIC design.
• Figure 3: (Left) Photograph of the KCU105 development board with the custom FMC ASIC carrier with ASIC wire bonded to it. (Right) Zoomed in photograph of the 130nm CMOS ASIC (5mm x 5mm).
• Figure 4: Photograph of the 130nm ASIC connected to a logic analyzer (left), and logic analyzer display of the eFPGA loaded with a simple 16-bit counter bitstream (right).
• Figure 5: Plot of the 130nm ASIC core voltage power draw versus clock frequency (left), and plot of the 130nm ASIC I/O voltage power draw versus clock frequency (right).