Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods
Aman Kumar, Mark Litterick, Samuele Candido
TL;DR
The paper addresses verification bottlenecks in complex RADAR-based SoCs by presenting a hybrid verification workflow that blends formal verification (FPV, CSR, CONN, CDC, UNR) with extensive simulation (UVM-based, GLS, AMS) and augments throughput with ML-driven regression (Xcelium ML). Key contributions include a requirements-driven vPlan for traceability, UPF-powered power verification integration, and demonstrated efficiency gains in verification throughput and sign-off timing. The study demonstrates high functional and protocol coverage in the simulated environment, early bug detection via formal methods, and substantial gains in regression efficiency through ML optimization. This work offers a practical, scalable framework for robust verification of advanced IoT/HMI SOCs, enabling faster time-to-market without compromising reliability.
Abstract
As the demand for Internet of Things (IoT) and Human-to-Machine Interaction (HMI) increases, modern System-on-Chips (SoCs) offering such solutions are becoming increasingly complex. This intricate design poses significant challenges for verification, particularly when time-to-market is a crucial factor for consumer electronics products. This paper presents a case study based on our work to verify a complex Radio Detection And Ranging (RADAR) based SoC that performs on-chip sensing of human motion with millimetre accuracy. We leverage both formal and simulation-based methods to complement each other and achieve verification sign-off with high confidence. While employing a requirements-driven flow approach, we demonstrate the use of different verification methods to cater to multiple requirements and highlight our know-how from the project. Additionally, we used Machine Learning (ML) based methods, specifically the Xcelium ML tool from Cadence, to improve verification throughput.