Distributed Architecture for FPGA-based Superconducting Qubit Control

TL;DR

This paper tackles the need for real-time, low-latency classical control in superconducting qubit systems and presents a distributed FPGA-based architecture integrated with QubiC 2.0 to support mid-circuit measurements and feedforward. It introduces a bank of lightweight processor cores that drive DDS-based signal generators and a function processor, plus a modular QubiC-IR compiler that maps gate- and pulse-level programs to the distributed ISA. The work provides a comprehensive hardware/software stack, including a gated assembly language, a JSON-based IR, and scheduling passes, and demonstrates scalability on an 8-qubit Trailblazer system with a mid-circuit teleportation experiment. The results show successful dynamic circuit execution with measurement-based control and conditional operations, while acknowledging residual errors from dephasing and readout crosstalk. Overall, the open-source architecture enables flexible, low-latency superconducting-qubit control and paves the way for advanced real-time quantum algorithms and error-correction protocols.

Abstract

Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We have developed a custom FPGA-based processor architecture for QubiC, an open source platform for superconducting qubit control. Our architecture is distributed in nature, and consists of a bank of lightweight cores, each configured to control a small (1-3) number of signal generator channels. Each core is capable of executing parameterized control and readout pulses, as well as performing arbitrary control flow based on mid-circuit measurement results. We have also developed a modular compiler stack and domain-specific intermediate representation for programming the processor. Our representation allows users to specify circuits using both gate and pulse-level abstractions, and includes high-level control flow constructs (e.g. if-else blocks and loops). The compiler stack is designed to integrate with quantum software tools and programming languages, such as TrueQ, pyGSTi, and OpenQASM3. In this work, we will detail the design of both the processor and compiler stack, and demonstrate its capabilities with a quantum state teleportation experiment using transmon qubits at the LBNL Advanced Quantum Testbed.

Figures (13)

• Figure 1: Block diagram of the distributed architecture. In this example, each processor core is responsible for control and readout of a single qubit. Note that the measurement and state-discrimination signal chain exists outside the core, with the results fed directly into the function processor block.
• Figure 2: Processor core microarchitecture. Includes a register file, ALU, and instruction pointer for arithmetic and control flow instructions. All pulse triggers are referenced to the time_ref block, which is a counter that is reset at the beginning of program execution and can be incremented during runtime. All instructions are implemented as 128-bit words. Pulse fields are written to the Pulse Register block, and can be provided by values from the register file and/or instruction immediates. The pulse trigger is given by the c_strobe signal.
• Figure 3: General format for arithmetic and control flow instructions. The instruction type is given by the opcode. Bit 123 (r/i) is used to specify whether ALU input 0 is an instruction immediate or register value from the provided address. The inc_qclk instruction also follows this format, with only the opcode fields (127:120) and ALU input 0 provided.
• Figure 4: General format for pulse_write and pulse_write_trig instructions. Each pulse field (env, phase, amp, and freq) has two control bits; one for write enable and another to select register (from address in 119:116) or instruction immediate. In our implementation, the phase and amplitude are specified directly as scaled values, the frequency is provided as an address, and the envelope word specifies both the start address and envelope length. A 4-bit config word is provided for miscellaneous configuration parameters; this must be provided as an instruction immediate. The idle instruction also follows this format, but the only provided fields are the instruction opcode and the start time, which provides the timestamp after which to resume core execution.
• Figure 5: Example assembly code for single-qubit reset. This program initiates a readout on Q1, then conditionally plays a drive pulse depending on the measurement outcome. The assembly program is formatted as a Python/JSON dictionary, with the program for each processor core keyed by a tuple of channels controlled by that core. In this example, we are only using the qubit Q1, which is controlled by the ('Q1.qdrv', 'Q1.rdrv', 'Q1.rdlo') core.