KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology

TL;DR

This work tackles automatic transistor sizing in analog circuits by introducing KATO, a knowledge-alignment-and-transfer Bayesian optimization framework. It combines an automatically constructed Neural Kernel, Dual Embedding for cross-circuit transfer, and a Bandit mechanism to regulate transferred knowledge, all integrated into a multi-objective acquisition ensemble (MACE) for robust optimization under constraints. Empirical results on OpAmp and Bandgap circuits show AVIS achieving up to 2x simulation reduction and up to 1.2x design improvement, with strong transfer-learning gains across technology nodes and circuit topologies. The approach enables practical, scalable design improvements across design families and technology nodes, while acknowledging limitations and areas for tuning in broader settings.

Abstract

Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.

Figures (4)

• Figure 1: Schematic of the evaluation circuits
• Figure 2: Transistor sizing by optimizing FOM
• Figure 3: Transistor sizing by constrained optimization
• Figure 4: Transistor sizing constrained optimization with of designs and technology node