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Parallel AIG Refactoring via Conflict Breaking

Ye Cai, Zonglin Yang, Liwei Ni, Junfeng Liu, Biwei Xie, Xingquan Li

TL;DR

This paper tackles the slowdown of sequential AIG-based logic refactoring in EDA by identifying two conflict types that arise in parallelization and introducing a levelization-based scheduler with a four-stage parallel framework. The method separates work into scheduling, parallel refactoring, replacement, and post-processing to exploit node-level parallelism while preserving topological order, employing per-thread local storage and MFFC recycling to mitigate data races and dependency conflicts. Empirical results on large AIGs expanded from EPFL benchmarks show an average speedup of $28x$ on up to $64$ cores with QoR comparable to the ABC baseline, demonstrating scalable performance without sacrificing optimization quality. The work offers a practical approach to parallelizing AIG refactoring, enabling faster EDA optimization for very large IC designs on multi-core platforms.

Abstract

Algorithm parallelization to leverage multi-core platforms for improving the efficiency of Electronic Design Automation~(EDA) tools plays a significant role in enhancing the scalability of Integrated Circuit (IC) designs. Logic optimization is a key process in the EDA design flow to reduce the area and depth of the circuit graph by finding logically equivalent graphs for substitution, which is typically time-consuming. To address these challenges, in this paper, we first analyze two types of conflicts that need to be handled in the parallelization framework of refactoring And-Inverter Graph~(AIG). We then present a fine-grained parallel AIG refactoring method, which strikes a balance between the degree of parallelism and the conflicts encountered during the refactoring operations. Experiment results show that our parallel refactor is 28x averagely faster than the sequential algorithm on large benchmark tests with 64 physical CPU cores, and has comparable optimization quality.

Parallel AIG Refactoring via Conflict Breaking

TL;DR

This paper tackles the slowdown of sequential AIG-based logic refactoring in EDA by identifying two conflict types that arise in parallelization and introducing a levelization-based scheduler with a four-stage parallel framework. The method separates work into scheduling, parallel refactoring, replacement, and post-processing to exploit node-level parallelism while preserving topological order, employing per-thread local storage and MFFC recycling to mitigate data races and dependency conflicts. Empirical results on large AIGs expanded from EPFL benchmarks show an average speedup of on up to cores with QoR comparable to the ABC baseline, demonstrating scalable performance without sacrificing optimization quality. The work offers a practical approach to parallelizing AIG refactoring, enabling faster EDA optimization for very large IC designs on multi-core platforms.

Abstract

Algorithm parallelization to leverage multi-core platforms for improving the efficiency of Electronic Design Automation~(EDA) tools plays a significant role in enhancing the scalability of Integrated Circuit (IC) designs. Logic optimization is a key process in the EDA design flow to reduce the area and depth of the circuit graph by finding logically equivalent graphs for substitution, which is typically time-consuming. To address these challenges, in this paper, we first analyze two types of conflicts that need to be handled in the parallelization framework of refactoring And-Inverter Graph~(AIG). We then present a fine-grained parallel AIG refactoring method, which strikes a balance between the degree of parallelism and the conflicts encountered during the refactoring operations. Experiment results show that our parallel refactor is 28x averagely faster than the sequential algorithm on large benchmark tests with 64 physical CPU cores, and has comparable optimization quality.
Paper Structure (13 sections, 2 theorems, 5 figures, 3 tables)

This paper contains 13 sections, 2 theorems, 5 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Background
  4. Analyses of Parallel Refactor Design
  5. method
  6. Work Scheduler
  7. Evaluation
  8. Replacement
  9. experiment
  10. Setup
  11. Parallel AIG Refactor Scalability.
  12. Parallel AIG Refactor QoR
  13. conclusion

Key Result

Theorem 1

If one node is contained in both MFFCs of node $x$ and node $y$, there is a path between $x$ and $y$. (The path here only allows one-way transmission from PIs to POs). $\square$

Figures (5)

  • Figure 1: An example of an AIG (left) and its optimised AIG after refactor (right), where the functions $f=\neg (a \wedge b \wedge c) \wedge d$, and $g=0$. The paths from node $b$ to node $3$ are a pair of reconvergence paths.
  • Figure 2: Example of the conflicts caused by data dependency.
  • Figure 3: The framework of the proposed parallel AIG refactoring.
  • Figure 4: Example of MFFC node recycling and deletion.
  • Figure 5: Scalability of parallel refactor compared with ABC command refactor -l 0.

Theorems & Definitions (4)

  • Theorem 1
  • Proof
  • Theorem 2
  • Proof