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Enhancing ASIC Technology Mapping via Parallel Supergate Computing

Ye Cai, Zonglin Yang, Liwei Ni, Biwei Xie, Xingquan Li

TL;DR

The paper tackles the time-intensive challenge of generating large numbers of supergates during ASIC technology mapping by introducing a parallel supergate computing framework. It leverages input-constrained patterns and a combination of recursive backtracking with multi-threaded processing to simultaneously generate and filter candidate supergates, thereby accelerating the mapping flow while preserving or improving delay QoR. Key contributions include a formalization of $k$-feasible cuts and Boolean matching in a parallel setting, a concrete pre-processing and post-processing pipeline, and complexity-aware design that demonstrates up to a 4x runtime speedup with 32 threads and about a 10.1% delay reduction in QoR on EPFL benchmarks. The approach shows meaningful practical impact for large-scale ASIC design by reducing mapping time without sacrificing, and in some cases improving, mapping quality when using an expanded supergate library.

Abstract

With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend. The optimization of delay reduction is a crucial factor for ASIC technology mapping, and supergate technology proves to be an effective method for achieving this in EDA tools flow. However, we have observed that increasing the number of generated supergates can reduce delay, but this comes at the cost of an exponential increase in computation time. In this paper, we propose a parallel supergate computing method that addresses the tradeoff between time-consuming and delay optimization. The proposed method utilizes the input-constrained supergate pattern to parallelly generate the supergate candidates, and then filter the valid supergates as the results. Experiment results show the efficiency of the proposed method, for example, it can attain the improvement of 4x speedup in computation time and 10.1 in delay reduction with 32 threads.

Enhancing ASIC Technology Mapping via Parallel Supergate Computing

TL;DR

The paper tackles the time-intensive challenge of generating large numbers of supergates during ASIC technology mapping by introducing a parallel supergate computing framework. It leverages input-constrained patterns and a combination of recursive backtracking with multi-threaded processing to simultaneously generate and filter candidate supergates, thereby accelerating the mapping flow while preserving or improving delay QoR. Key contributions include a formalization of -feasible cuts and Boolean matching in a parallel setting, a concrete pre-processing and post-processing pipeline, and complexity-aware design that demonstrates up to a 4x runtime speedup with 32 threads and about a 10.1% delay reduction in QoR on EPFL benchmarks. The approach shows meaningful practical impact for large-scale ASIC design by reducing mapping time without sacrificing, and in some cases improving, mapping quality when using an expanded supergate library.

Abstract

With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend. The optimization of delay reduction is a crucial factor for ASIC technology mapping, and supergate technology proves to be an effective method for achieving this in EDA tools flow. However, we have observed that increasing the number of generated supergates can reduce delay, but this comes at the cost of an exponential increase in computation time. In this paper, we propose a parallel supergate computing method that addresses the tradeoff between time-consuming and delay optimization. The proposed method utilizes the input-constrained supergate pattern to parallelly generate the supergate candidates, and then filter the valid supergates as the results. Experiment results show the efficiency of the proposed method, for example, it can attain the improvement of 4x speedup in computation time and 10.1 in delay reduction with 32 threads.
Paper Structure (30 sections, 3 equations, 8 figures, 2 tables, 2 algorithms)

This paper contains 30 sections, 3 equations, 8 figures, 2 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Basic Notations
  4. Boolean Function
  5. And-Inverter Graph
  6. Standard Cell
  7. Supergate
  8. Basic Concepts
  9. $k$-feasible Cut
  10. Boolean Matching.
  11. Motivation and Problem Formulation
  12. ASIC Technology Mapping Flow
  13. Motivation Experiment
  14. Problem Formulation
  15. Proposed Methodology
  16. ...and 15 more sections

Figures (8)

  • Figure 1: The illustration of the 4-feasible cut enumeration procedure on an AIG format Boolean network. Each node is assigned the trivial cut first, then the iteratively merging operation is performed following the bottom-up direction.
  • Figure 2: The illustration of the standard cell and supergate computing. The (a) and (b) show the attributes of the standard cells, while (b) and (c) show the example of supergate computing.
  • Figure 3: The illustration of ASIC technology mapping flow with the support of the supergate computing flow targeting the AIG circuits.
  • Figure 4: The framework of the proposed parallel supergate computing.
  • Figure 5: The illustration of the experiment results.
  • ...and 3 more figures

Theorems & Definitions (2)

  • Definition 1: continuous-input candidate
  • Definition 2: discontinuous-input candidate