EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration

TL;DR

EasyACIM introduces a fully automated end-to-end flow for ACIM by proposing a synthesizable architecture that enables flexible $H$, $W$, $L$, and $B_{ADC}$ settings and integrating a MOGA-based Pareto-frontier explorer with a template-based hierarchical placer/router. The framework uses a QR compute model to balance robustness and extensibility, and derives a multi-objective estimation (SNR, throughput, energy, area) to guide NSGA-II optimization toward high-quality Pareto-optimal ACIM configurations. Experimental results on a TSMC28 PDK demonstrate rapid exploration (≈30 minutes per array size) and efficient layout generation, achieving energy efficiencies from $50$ to $750$ TOPS/W and area from $1500$ to $7500\,\text{F}^2$/bit, with competitive performance versus SOTA ACIMs. The work significantly accelerates ACIM design cycles and broadens viable application scenarios through an agile, end-to-end automated workflow.

Abstract

Analog Computing-in-Memory (ACIM) is an emerging architecture to perform efficient AI edge computing. However, current ACIM designs usually have unscalable topology and still heavily rely on manual efforts. These drawbacks limit the ACIM application scenarios and lead to an undesired time-to-market. This work proposes an end-to-end automated ACIM based on a synthesizable architecture (EasyACIM). With a given array size and customized cell library, EasyACIM can generate layouts for ACIMs with various design specifications end-to-end automatically. Leveraging the multi-objective genetic algorithm (MOGA)-based design space explorer, EasyACIM can obtain high-quality ACIM solutions based on the proposed synthesizable architecture, targeting versatile application scenarios. The ACIM solutions given by EasyACIM have a wide design space and competitive performance compared to the state-of-the-art (SOTA) ACIMs.

Figures (10)

• Figure 1: Unscalable ACIM macro and various scenarios.
• Figure 2: In-memory compute models: (a) QS (b) IS (c) QR.
• Figure 3: Basic grid-based placement and routing.
• Figure 4: Overview of EasyACIM.
• Figure 5: Timing diagram of the synthesizable ACIM.