STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems

TL;DR

STRELA addresses the need for energy-efficient embedded acceleration by introducing an elastic coarse-grained reconfigurable architecture (CGRA) tightly integrated with a low-power RISC-V SoC. The approach combines memory streaming nodes with an elastic, conditionally-capable CGRA to execute both data-driven and control-driven kernels, employing mapping strategies for one-shot and multi-shot workloads. Key contributions include a redesigned microarchitecture with Elastic Buffers, Branch/Merge control flow, and a configuration scheme that supports large kernels without private CGRA memories, plus an integration on the xheep platform with hardware- and software-driven energy-saving mechanisms. Empirical results show up to 1.22 GOPs peak performance and up to 115.96 MOPs/mW energy efficiency, demonstrating substantial improvements over prior CGRAs in embedded contexts and providing practical guidance for compiler/mapping support in real-world edge applications.

Abstract

Reconfigurable computing offers a good balance between flexibility and energy efficiency. When combined with software-programmable devices such as CPUs, it is possible to obtain higher performance by spatially distributing the parallelizable sections of an application throughout the reconfigurable device while the CPU is in charge of control-intensive sections. This work introduces an elastic Coarse-Grained Reconfigurable Architecture (CGRA) integrated into an energy-efficient RISC-V-based SoC designed for the embedded domain. The microarchitecture of CGRA supports conditionals and irregular loops, making it adaptable to domain-specific applications. Additionally, we propose specific mapping strategies that enable the efficient utilization of the CGRA for both simple applications, where the fabric is only reconfigured once (one-shot kernel), and more complex ones, where it is necessary to reconfigure the CGRA multiple times to complete them (multi-shot kernels). Large kernels also benefit from the independent memory nodes incorporated to streamline data accesses. Due to the integration of CGRA as an accelerator of the RISC-V processor enables a versatile and efficient framework, providing adaptability, processing capacity, and overall performance across various applications. The design has been implemented in TSMC 65 nm, achieving a maximum frequency of 250 MHz. It achieves a peak performance of 1.22 GOPs computing one-shot kernels and 1.17 GOPs computing multi-shot kernels. The best energy efficiency is 72.68 MOPs/mW for one-shot kernels and 115.96 MOPs/mW for multi-shot kernels. The design integrates power and clock-gating techniques to tailor the architecture to the embedded domain while maintaining performance. The best speed-ups are 17.63x and 18.61x for one-shot and multi-shot kernels. The best energy savings in the SoC are 9.05x and 11.10x for one-shot and multi-shot kernels.

Figures (8)

• Figure 1: Design structure.
• Figure 2: Microarchitecture of the fu and its output.
• Figure 3: Microarchitecture of the fu data and control inputs.
• Figure 4: Microarchitecture of the pe inputs and outputs.
• Figure 5: dfg examples.