Pseudo-random generators using linear feedback shift registers with output extraction

TL;DR

The paper investigates pseudo-random generators built from linear feedback shift registers (LFSRs) by applying different extraction schemes to derive output bits: a von Neumann extractor, a three-bit extractor on an extended LFSR, and a run extractor interpreted both as a triplet-based and a run-length mechanism. Using 16-bit LFSRs, it evaluates statistical randomness via balanced bit streams, low correlations, and favorable linear complexity, while quantifying output efficiencies of $1/4$, $5/12$, and $1/2$ respectively; all tested variants pass relevant randomness tests such as FIPS 140-1. The study demonstrates that higher extraction efficiency comes at reduced cryptographic strength, and discusses potential extensions (e.g., a four-bit extractor with $17/32$ efficiency) to widen practical applicability. Overall, the results show that LFSR-based generators with well-chosen extraction logic can yield high-quality, long-period pseudo-random streams suitable for cryptographic key streams, provided cryptographic strength requirements are carefully managed.

Abstract

The use of three extractors, fed by linear feedback shift registers (LFSR) for generating pseudo-random bit streams is investigated. Specifically, a standard LFSR is combined with a von Neumann extractor, a modified LFSR, extended by the all-zero state, is combined with an output logic, which translates every three bits from the LFSR into up to two output bits and a run extraction of the input bit stream into single output bits are investigated. The latter two achieve better efficiency in using bits from the primary bit stream, the last one reaches 50\%. Compared to other generator logics, the three extractors investigated are less performant in terms of their cryptographic strength. However, the focus of this report is on the quality of the pseudo-random bit stream in comparison to really random bits and on the efficiency of using the bits of the primary stream from the LFSR and generating valid output bits, while fulfilling a minimum cryptographic strength only, beyond that of the pure LFSR.

Figures (13)

• Figure 1: Standard Fibonacci-type 16-bit LFSR with a period of $2^{16}-1$ internal states
• Figure 2: Pseudo-random generator using a standard LFSR in combination with a von Neumann extractor
• Figure 3: Extended Fibonacci-type 16-bit LFSR with a period of $2^{16}$ internal states
• Figure 4: Pseudo-random generator using an extended LFSR in combination with a three-bit extractor
• Figure 5: Pseudo-random generator using a standard LFSR in combination with a run extractor (three-bit interpretation)