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SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation

Deepak Vungarala, Mahmoud Nazzal, Mehrdad Morsali, Chao Zhang, Arnob Ghosh, Abdallah Khreishah, Shaahin Angizi

TL;DR

SA-DS tackles the lack of specialized datasets for LLM-driven hardware accelerator design by providing a Gemmini-based, spatial-array dataset paired with natural-language descriptions and Chisel HDL, released under an MIT license. It proposes an end-to-end framework combining prompt design, in-context learning, and a verification pipeline (RTL-GDSII, functional checks, and PPA evaluation) with a feedback loop for iterative improvement. Empirically, SA-DS outperforms a baseline HLSD dataset across multiple LLMs in both single-shot and multi-shot settings, indicating improved design quality and reduced revision effort. The work enables rapid, configurable exploration of DNN accelerator architectures within the Chipyard/Gemmini ecosystem and invites further research in fine-tuning, prompt engineering, and optimization for hardware design tasks.

Abstract

In the ever-evolving landscape of Deep Neural Networks (DNN) hardware acceleration, unlocking the true potential of systolic array accelerators has long been hindered by the daunting challenges of expertise and time investment. Large Language Models (LLMs) offer a promising solution for automating code generation which is key to unlocking unprecedented efficiency and performance in various domains, including hardware descriptive code. The generative power of LLMs can enable the effective utilization of preexisting designs and dedicated hardware generators. However, the successful application of LLMs to hardware accelerator design is contingent upon the availability of specialized datasets tailored for this purpose. To bridge this gap, we introduce the Systolic Array-based Accelerator Data Set (SA-DS). SA-DS comprises a diverse collection of spatial array designs following the standardized Berkeley's Gemmini accelerator generator template, enabling design reuse, adaptation, and customization. SA-DS is intended to spark LLM-centered research on DNN hardware accelerator architecture. We envision that SA-DS provides a framework that will shape the course of DNN hardware acceleration research for generations to come. SA-DS is open-sourced under the permissive MIT license at https://github.com/ACADLab/SA-DS.git}{https://github.com/ACADLab/SA-DS.

SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation

TL;DR

SA-DS tackles the lack of specialized datasets for LLM-driven hardware accelerator design by providing a Gemmini-based, spatial-array dataset paired with natural-language descriptions and Chisel HDL, released under an MIT license. It proposes an end-to-end framework combining prompt design, in-context learning, and a verification pipeline (RTL-GDSII, functional checks, and PPA evaluation) with a feedback loop for iterative improvement. Empirically, SA-DS outperforms a baseline HLSD dataset across multiple LLMs in both single-shot and multi-shot settings, indicating improved design quality and reduced revision effort. The work enables rapid, configurable exploration of DNN accelerator architectures within the Chipyard/Gemmini ecosystem and invites further research in fine-tuning, prompt engineering, and optimization for hardware design tasks.

Abstract

In the ever-evolving landscape of Deep Neural Networks (DNN) hardware acceleration, unlocking the true potential of systolic array accelerators has long been hindered by the daunting challenges of expertise and time investment. Large Language Models (LLMs) offer a promising solution for automating code generation which is key to unlocking unprecedented efficiency and performance in various domains, including hardware descriptive code. The generative power of LLMs can enable the effective utilization of preexisting designs and dedicated hardware generators. However, the successful application of LLMs to hardware accelerator design is contingent upon the availability of specialized datasets tailored for this purpose. To bridge this gap, we introduce the Systolic Array-based Accelerator Data Set (SA-DS). SA-DS comprises a diverse collection of spatial array designs following the standardized Berkeley's Gemmini accelerator generator template, enabling design reuse, adaptation, and customization. SA-DS is intended to spark LLM-centered research on DNN hardware accelerator architecture. We envision that SA-DS provides a framework that will shape the course of DNN hardware acceleration research for generations to come. SA-DS is open-sourced under the permissive MIT license at https://github.com/ACADLab/SA-DS.git}{https://github.com/ACADLab/SA-DS.
Paper Structure (5 sections, 5 figures, 2 tables)

This paper contains 5 sections, 5 figures, 2 tables.

Table of Contents

  1. Introduction
  2. SA-DS and An Envisioned Framework
  3. SA-DS Sample Creation
  4. Experimental Results
  5. Conclusion

Figures (5)

  • Figure 1: Gemmini architectural template for ASIC accelerator design genc2021gemmini .
  • Figure 2: An envisioned framework for utilizing SA-DS.
  • Figure 3: An example of one category and its design space parameters in the proposed SA-DS.
  • Figure 4: The frequency of sample in SA-DS in terms of (a) function units in each category based on the Data flow for systolic arrays, (b) Function units available individually or in combination with the others.
  • Figure 5: (a) The data point structure, (b) An example prompt and the output generated by the LLM.