Towards scalable cryogenic quantum dot biasing using memristor-based DC sources

TL;DR

This work addresses scalable in-situ biasing of silicon quantum dots at cryogenic temperatures using memristor-based DC sources. It demonstrates a cryo-compatible op-amp TIAs with memristor feedback and a programmable DC source prototype, achieving 0.25–1 V biasing with 10 mV steps at 1.2 K, albeit with limited resolution and increased noise compared with room temperature. Scaling analyses show that monolithic integration of memristors with 65 nm CMOS and other eNVM technologies can reduce per-source power to the µW range and enable thousands to approaching a million DC sources at 4.2 K, depending on technology. The results suggest a viable path toward large-scale, low-noise quantum dot biasing essential for future scalable quantum processors.

Abstract

Cryogenic memristor-based DC sources offer a promising avenue for in situ biasing of quantum dot arrays. In this study, we present experimental results and discuss the scaling potential for such DC sources. We first demonstrate the operation of a commercial discrete operational amplifier down to 1.2K which is used on the DC source prototype. Then, the tunability of the memristor-based DC source is validated by performing several 250mV-DC sweeps with a resolution of 10mV at room temperature and at 1.2K. Additionally, the DC source prototype exhibits a limited output drift of $\approx1\mathrm{μVs^{-1}}$ at 1.2K. This showcases the potential of memristor-based DC sources for quantum dot biasing. Limitations in power consumption and voltage resolution using discrete components highlight the need for a fully integrated and scalable complementary metal-oxide-semiconductor-based (CMOS-based) approach. To address this, we propose to monolithically co-integrate emerging non-volatile memories (eNVMs) and 65nm CMOS circuitry. Simulations reveal a reduction in power consumption, down to $\mathrm{10μW}$ per DC source and in footprint. This allows for the integration of up to one million eNVM-based DC sources at the 4.2K stage of a dilution fridge, paving the way for near term large-scale quantum computing applications.

Figures (5)

• Figure 1: Schematic view of the memristor-based DC source prototype. The required interconnects between cryogenic temperatures and room temperature electronics are shown as small black squares. Analog switches are used to connect the memristors to APMUs or to short them to provide resistive feedback to the OpAmp.
• Figure 2: Cryogenic characterization of the AD8605 OpAmpa. Schematic of the cryogenic TIA circuit based on the AD8605 OpAmp. $R_\textrm{fb}/R_\textrm{in}$ define the gain of the TIA with $R_\textrm{fb}=2kΩ$ and $R_\textrm{in}=1kΩ$. b. FR-4 PCB implementation of the AD8605 TI circuits. c. DC characterization of the TIA behavior at 1.2K, 35K and 300K. d. Fitted closed-loop gain (blue) and idle current (red) of the AD8605 OpAmp from 1.2K to 300K. The idle current is defined as the current consumption for $V_\textrm{in}=0V$
• Figure 3: Experimental setup for the cryogenic memristor-based DC source.a. Block schematic of the experimental setup used to validate the cryogenic memristor-based DC source. b. 4-layer FR-4 PCB implementation of the memristor-based DC source prototype. A custom chip carrier with a wire-bonded memristor chip is connected to the prototype PCB. c. Flowchart of the DC source prototype programming.
• Figure 4: Electrical characteristics of the memristor-based DC source prototype.a. A 250mV voltage sweep between 0.4V and 0.65V with a resolution of 10mV at 300K. The experiment was performed with 2 memristors connected in parallel in the feedback loop of the TIA circuit, with $V_\textrm{in}=0.25V$ and $V_\textrm{dd}=-V_\textrm{ss}=2.7V$. The voltage sweep is performed 10 times, with each point representing the mean voltage programmed while the error bars show the programming error. The mean resolution error (MRE) is shown in the inset. b. Stability of three intermediary programmed voltages at 300K. Each programmed voltage is fitted by linear regression ($aV+b$) to verify the drift of the programmed voltage. The three insets depict the variability of each stable programmed voltage. c. Ten 250mV voltage sweeps between 0.4V and 0.65V with a resolution of 10mV at 1.2K. The experiment was performed with 2 memristors connected in parallel in the feedback loop of the TIA circuit, with $V_\textrm{in}=75mV$ and $V_\textrm{dd}=-V_\textrm{ss}=3.0V$. The inset shows the MRE for this measurement. d. Stability of three programmed voltages at 1.2K. The three insets depict the variability of each stable programmed voltage.
• Figure 5: eNVM-based DC source scaling simulations.a. The operational amplifier schematic based on a two-stage Miller topology. One or multiple eNVM can be placed between the V$_\textrm{in}$ and V$_{\textrm{out}}$ nodes to enable the tunability of the DC source. A single fixed resistor R$_{\textrm{in}}$ is placed after the V$_\textrm{in}$ node to allow transimpedance amplification. b. DC characteristics of the operational amplifier for a feedback resistance ranging from 10kΩ to 100kΩ. The circuit parameters used for this simulation are reported in \ref{['tab:params']}. c Feedback resistance scaling simulation. Larger resistances results in a decrease of the bias current I$_\textrm{B}$, leading to a power consumption decrease. d Maximum number of eNVM-based DC sources integrable at the 4.2K stage of a Bluefors XLD dilution fridge i.e., a 1.5W cooling power. The dashed black lines show the minimum resistance of different eNVM technologies.