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Benchmarking logical three-qubit quantum Fourier transform encoded in the Steane code on a trapped-ion quantum computer

Karl Mayer, Ciarán Ryan-Anderson, Natalie Brown, Elijah Durso-Sabina, Charles H. Baldwin, David Hayes, Joan M. Dreiling, Cameron Foltz, John P. Gaebler, Thomas M. Gatterman, Justin A. Gerber, Kevin Gilmore, Dan Gresh, Nathan Hewitt, Chandler V. Horst, Jacob Johansen, Tanner Mengle, Michael Mills, Steven A. Moses, Peter E. Siegfried, Brian Neyenhuis, Juan Pino, Russell Stutz

TL;DR

This work tackles the challenge of benchmarking quantum error correction–encoded circuits by implementing a three-qubit QFT encoded in the [[7,1,3]] Steane code on trapped-ion hardware. It combines component-level benchmarking (randomized benchmarking for logical CNOT and teleportation-based logical T) with a system-level encoded QFT, explored via two different logical-T implementations and Hofmann-based fidelity bounds across two mutually unbiased bases. The study finds that logical two-qubit gates perform near the physical break-even, while non-Clifford gates and memory effects dominate logical QFT error, with post-selection providing partial improvement but not overcoming unencoded QFT on current devices. The results highlight the gap between component-level and system-level performance, underscoring the need for higher-distance codes and fault-tolerant non-Clifford operations, and they establish a practical, extensible framework (SLR) for logical benchmarking across platforms. Overall, the work advances the experimental evaluation of quantum error correction at the logical level and outlines concrete directions for achieving scalable, fault-tolerant quantum computation.

Abstract

We implement logically encoded three-qubit circuits for the quantum Fourier transform (QFT), using the [[7,1,3]] Steane code, and benchmark the circuits on the Quantinuum H2-1 trapped-ion quantum computer. The circuits require multiple logical two-qubit gates, which are implemented transversally, as well as logical non-Clifford single-qubit rotations, which are performed by non-fault-tolerant state preparation followed by a teleportation gadget. First, we benchmark individual logical components using randomized benchmarking for the logical two-qubit gate, and a Ramsey-type experiment for the logical $T$ gate. We then implement the full QFT circuit, using two different methods for performing a logical control-$T$, and benchmark the circuits by applying it to each basis state in a set of bases that is sufficient to lower bound the process fidelity. We compare the logical QFT benchmark results to predictions based on the logical component benchmarks.

Benchmarking logical three-qubit quantum Fourier transform encoded in the Steane code on a trapped-ion quantum computer

TL;DR

This work tackles the challenge of benchmarking quantum error correction–encoded circuits by implementing a three-qubit QFT encoded in the [[7,1,3]] Steane code on trapped-ion hardware. It combines component-level benchmarking (randomized benchmarking for logical CNOT and teleportation-based logical T) with a system-level encoded QFT, explored via two different logical-T implementations and Hofmann-based fidelity bounds across two mutually unbiased bases. The study finds that logical two-qubit gates perform near the physical break-even, while non-Clifford gates and memory effects dominate logical QFT error, with post-selection providing partial improvement but not overcoming unencoded QFT on current devices. The results highlight the gap between component-level and system-level performance, underscoring the need for higher-distance codes and fault-tolerant non-Clifford operations, and they establish a practical, extensible framework (SLR) for logical benchmarking across platforms. Overall, the work advances the experimental evaluation of quantum error correction at the logical level and outlines concrete directions for achieving scalable, fault-tolerant quantum computation.

Abstract

We implement logically encoded three-qubit circuits for the quantum Fourier transform (QFT), using the [[7,1,3]] Steane code, and benchmark the circuits on the Quantinuum H2-1 trapped-ion quantum computer. The circuits require multiple logical two-qubit gates, which are implemented transversally, as well as logical non-Clifford single-qubit rotations, which are performed by non-fault-tolerant state preparation followed by a teleportation gadget. First, we benchmark individual logical components using randomized benchmarking for the logical two-qubit gate, and a Ramsey-type experiment for the logical gate. We then implement the full QFT circuit, using two different methods for performing a logical control-, and benchmark the circuits by applying it to each basis state in a set of bases that is sufficient to lower bound the process fidelity. We compare the logical QFT benchmark results to predictions based on the logical component benchmarks.
Paper Structure (17 sections, 20 equations, 13 figures, 5 tables)

This paper contains 17 sections, 20 equations, 13 figures, 5 tables.

Figures (13)

  • Figure 1: Two versions of a teleportation gadget for performing a logical phase gate, which we refer to as (a) method one and (b) method two. The circuits use an ancilla prepared in $\ket{\theta}=\frac{1}{\sqrt{2}}(\ket{0}+e^{i\theta}\ket{1})$, and output the state $P(\theta)\ket{\psi}$, where $P(\theta)=\mathrm{diag}(1,e^{i\theta})$. Taking $\theta=\pi/4$ yields the $T$ gate.
  • Figure 2: Fault-tolerant repeat-until-success $\ket{\overline{0}}$ initialization circuit. If the ancilla qubit measurement result is '0', then the initialization succeeds. Otherwise, the circuit is repeated, up to a limit of three repetitions.
  • Figure 3: Non-fault-tolerant logical encoding circuit for the Steane code. The final qubit in the quantum register is prepared in $\ket{\psi}$ and the resulting logical state is $\ket{\overline{\psi}}$.
  • Figure 4: Logical two-qubit RB decay curves for the devices H1-1 and H2-1. Ten random circuits per sequence length were chosen, and all circuits were run with 100 shots and submitted in a random order. The curves are fit to Eq. \ref{['eq: RB decay']}, and the estimated average fidelities per logical CNOT are listed in Table \ref{['tab: benchmarks']}.
  • Figure 5: Logical $T$ gate benchmarking decay curves for the device H2-1 and the two methods for the teleportation gadget shown in Fig. \ref{['fig: teleporation gadget2']}. Solid lines are fit to the raw data and dashed lines to the data including post-selection on the syndromes obtained from the logical measurement in the teleportation gadgets (labeled P.S.). Ten random circuits per sequence length were chosen and all circuits were run with 100 shots and submitted in a random order. The curves are fit to Eq. \ref{['eq: T decay']}, and the estimated average fidelities per logical $T$ are listed in Table \ref{['tab: benchmarks']}.
  • ...and 8 more figures