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Quantum Tunneling: From Theory to Error-Mitigated Quantum Simulation

Sorana Catrina, Alexandra Băicoianu

TL;DR

This work develops and demonstrates an end-to-end workflow for simulating quantum tunneling on quantum hardware, integrating theory, hardware-aware circuit design, and error mitigation. By discretizing space and time, employing Suzuki–Trotter decomposition, and using the Quantum Fourier Transform to switch to momentum space, the authors implement kinetic and potential operators and prepare Gaussian initial states within a hardware-conscious framework. They show that Zero Noise Extrapolation and Readout Error Mitigation substantially improve results on real devices, achieving transmission probabilities within a small margin of the ideal and using multiprogramming to maximize chip utilization. The extended experiments with 2- and 6-qubit setups illustrate the method's scalability and provide practical guidelines for hardware-aware quantum simulations in the NISQ era, with broad implications for quantum chemistry and open-system dynamics.

Abstract

Ever since the discussions about a possible quantum computer arised, quantum simulations have been at the forefront of possible utilities and the task of quantum simulations is one that promises quantum advantage. In recent years, simulations of large molecules through VQE or dynamics of many-body spin Hamiltonians may be possible, and even able to achieve useful results with the use of error mitigation techniques. Simulating smaller models is also important, and currently, in the NISQ (Noisy intermediate-scale quantum) era, it is easier and less prone to errors. This current study encompasses the theoretical background and the hardware aware circuit implementation of a quantum tunneling simulation. Specifically, this study presents the theoretical background needed for such implementation and highlights the main steps of development. Building on classic approaches of quantum tunneling simulations, this study improves the result of such simulations by employing error mitigation techniques (ZNE and REM) and uses them in conjunction with multiprogramming of the quantum chip for solving the hardware under-utilization problem that arises in such contexts. Moreover, we highlight the need for hardware-aware circuit implementations and discuss these considerations in detail to give an end-to-end workflow overview of quantum simulations.

Quantum Tunneling: From Theory to Error-Mitigated Quantum Simulation

TL;DR

This work develops and demonstrates an end-to-end workflow for simulating quantum tunneling on quantum hardware, integrating theory, hardware-aware circuit design, and error mitigation. By discretizing space and time, employing Suzuki–Trotter decomposition, and using the Quantum Fourier Transform to switch to momentum space, the authors implement kinetic and potential operators and prepare Gaussian initial states within a hardware-conscious framework. They show that Zero Noise Extrapolation and Readout Error Mitigation substantially improve results on real devices, achieving transmission probabilities within a small margin of the ideal and using multiprogramming to maximize chip utilization. The extended experiments with 2- and 6-qubit setups illustrate the method's scalability and provide practical guidelines for hardware-aware quantum simulations in the NISQ era, with broad implications for quantum chemistry and open-system dynamics.

Abstract

Ever since the discussions about a possible quantum computer arised, quantum simulations have been at the forefront of possible utilities and the task of quantum simulations is one that promises quantum advantage. In recent years, simulations of large molecules through VQE or dynamics of many-body spin Hamiltonians may be possible, and even able to achieve useful results with the use of error mitigation techniques. Simulating smaller models is also important, and currently, in the NISQ (Noisy intermediate-scale quantum) era, it is easier and less prone to errors. This current study encompasses the theoretical background and the hardware aware circuit implementation of a quantum tunneling simulation. Specifically, this study presents the theoretical background needed for such implementation and highlights the main steps of development. Building on classic approaches of quantum tunneling simulations, this study improves the result of such simulations by employing error mitigation techniques (ZNE and REM) and uses them in conjunction with multiprogramming of the quantum chip for solving the hardware under-utilization problem that arises in such contexts. Moreover, we highlight the need for hardware-aware circuit implementations and discuss these considerations in detail to give an end-to-end workflow overview of quantum simulations.
Paper Structure (39 sections, 32 equations, 23 figures, 2 tables, 1 algorithm)

This paper contains 39 sections, 32 equations, 23 figures, 2 tables, 1 algorithm.

Table of Contents

  1. Abstract
  2. Introduction
  3. Theoretical Background
  4. Quantum Tunneling
  5. Implementation considerations
  6. Discretizing time and space
  7. Implementing the operators
  8. The Kinetic Energy Operator
  9. Potential Energy Operator
  10. Quantum Fourier Transform
  11. Initial State
  12. Circuit Overview
  13. Four qubits Quantum Tunneling Simulation
  14. Running on hardware
  15. Introduction
  16. ...and 24 more sections

Figures (23)

  • Figure 1: $Z_1 \otimes Z_2$ Hamiltonian implementation using ancilla qubits
  • Figure 2: Full circuit overview
  • Figure 3: High level overview of 2 qubit operations
  • Figure 4: Implementation of x11x type potential
  • Figure 5: Each diagram reperesents a 4q noiseless simulation. The bottom image presents the profile of the potential, along with the initial position of the wave that can also be observed at timestep 0 of the diagram
  • ...and 18 more figures