Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design

TL;DR

The paper addresses the challenge that ADC energy and area can dominate Compute-In-Memory accelerators, motivating the need for architecture-level ADC modeling. It develops an open-source architecture-level model that estimates ADC energy and area from high-level parameters such as $N_{ADC}$, Throughput, $Tech$, and $ENOB$, combining Murmann-based throughput bounds for energy with a regression-based area predictor. The model is integrated into CiMLoop and evaluated on RAELLA CiM accelerators to demonstrate interpolation across design points and to illuminate tradeoffs between ADC resolution, throughput, and the number of ADCs. Key contributions include a best-case energy bound extension, an area model that ties to energy via a parsimonious relationship, and practical guidance for minimizing the accelerator energy-area product during design-space exploration.

Abstract

Analog Compute-in-Memory (CiM) accelerators use analog-digital converters (ADCs) to read the analog values that they compute. ADCs can consume significant energy and area, so architecture-level ADC decisions such as ADC resolution or number of ADCs can significantly impact overall CiM accelerator energy and area. Therefore, modeling how architecture-level decisions affect ADC energy and area is critical for performing architecture-level design space exploration of CiM accelerators. This work presents an open-source architecture-level model to estimate ADC energy and area. To enable fast design space exploration, the model uses only architecture-level attributes while abstracting circuit-level details. Our model enables researchers to quickly and easily model key architecture-level tradeoffs in accelerators that use ADCs.

Figures (5)

• Figure 1: The energy and area modeling pipeline.
• Figure 2: Published ADC throughput versus energy. Lines show energy bounds identified by the model and dots show published ADCs. ADC energy is limited by two bounds that are a function of throughput, ENOB, and technology node.
• Figure 3: Published ADC throughput versus area. Lines show predicted area and dots show published ADCs. As throughput increases, area first increases slowly, then quickly. This is because the two energy bounds influence area.
• Figure 4: Energy for varying utilization and analog sum size. Summing more analog values and reading the results with higher-ENOB ADCs (towards XL) consumes less energy with higher-utilization DNN layers.
• Figure 5: Accelerator energy-area product (EAP) versus number of ADCs for varying throughputs. The number of ADCs significantly impacts EAP, and the lowest-EAP number of ADCs depends on throughput requirements.