Learning to rank quantum circuits for hardware-optimized performance enhancement

TL;DR

Beyond delivering a new form of predictive quantum characterization, verification, and validation, the results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

Abstract

We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit ibmq_guadalupe device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

Figures (5)

• Figure 1: Circuit transpilation and the task of layout selection. (a) A representative initial circuit. Such circuits are unconstrained by hardware considerations, such as matching the device topology or consisting only of native gates. (b) The qubit connectivity graph of the initial circuit. Nodes represent the qubits appearing in (a) and edges represent 2-qubit gates. (c) The hardware-compatible circuit. Hardware transpilation transforms the initial circuit into a unitarily equivalent, hardware-compatible circuit. Shown here is the hardware-transpiled circuit corresponding to the initial circuit on the ibmq_guadalupe device (only a portion is shown for brevity). (d) The qubit connectivity graph of the hardware-transpiled circuit. Unlike the initial connectivity graph, the transpiled connectivity graph is a subgraph of the device topology (shown in (e)). The node labels correspond to the qubit labels in (d). (e) The layout is a map between circuit qubits and physical qubits. There are typically many such mappings; shown here is a subset of four layouts. The goal of layout selection is then to choose the best-performing layout for execution on the device.
• Figure 2: The importance of layout selection. (a) Distribution of the performance quality ratio between the median- and maximum-performing layouts as measured by the Hellinger fidelity, $H_F$, evaluated over large a data set of more than 6000 circuits (see the main text for more details about the data set). The inset shows a zoomed-in and higher-resolution plot for performance qualities between 0 and 60%. (The first bar in the inset has zero counts, i.e., the difference between the top and median performing layouts exceeded $4\%$ for all circuits.) (b) The number of layouts, averaged over 500 random initial circuits, as a function of the circuit width $n$. The markers indicate averages, and the shaded region indicates the range. The inset shows the average number of layouts as a function of $n/N$, the fraction of device qubits used. Note that these results assume bi-directional device graphs.
• Figure 3: Machine learning pipeline for layout selection. (a) Layout generation. Graphs indicate connectivity of ibmq_guadalupe device: graph nodes indicate qubits and colored nodes are guides to the eye indicating different layouts for a notional five-qubit circuit. Only three layouts, A-C, shown for visual clarity. Different layers represent sets of layouts for different initial circuits. Purple QPU icons indicate hardware execution. The black database icon indicates that data from hardware execution form a dataset. (b) Overview of training phase. Ordering of layouts is now set by ranking conducted using current state of model. Purple dashed arrows indicate mismatches between model prediction and true ranking determined by database. The lower arrow indicates an iterative loop to minimize loss function via model parameter updates (see Table \ref{['table:lossfunctions']}). (c) Overview of inference phase. The highest-ranking layout is selected for hardware execution, indicated by purple shading. There is no restriction that these layouts be present in the dataset, and in the primary use-case, the goal will be to predict layout rankings when the true ranking is unavailable
• Figure 4: Model performance. The performance of circuit score models trained on the loss functions listed in Table \ref{['table:lossfunctions']}, as measured by multiple evaluation metrics averaged over the test set. The win rate is measured against Mapomatic (MM). Note that a lower value is better for the normed rank (a) and selection error (b), whereas a higher value is better for the top-1 accuracy (c) and win rate (d). To account for statistical variations in the optimization and in the training/testing split, for each loss function 10 random seeds are used, and numerical values are averaged over these.
• Figure 5: Dataset statistics. (Top): The distribution of layout sizes (the number of ways that a given initial circuit can "fit" onto the device after hardware transpilation), according to algorithm. The number of layouts per circuit ranges from 2 to 46. (Bottom): The distribution of empirical Hellinger fidelities, also according to algorithm. Note that the details of each algorithm, such as the circuit width $n$ or the random graph used in the QAOA circuit were chosen to produce circuits whose Hellinger fidelities were not extreme (i.e., near 0 or near 1).