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Neuroevolving Electronic Dynamical Networks

Derek Whitley

TL;DR

The paper tackles the bottleneck of fitness evaluation in neuroevolution of continuous-time recurrent neural networks (CTRNNs), which require simulating time-evolving dynamics. It introduces a hardware-accelerated approach that embeds CTRNN evaluation on a Xilinx ZCU102 FPGA, using forward-Euler integration, 16-bit fixed-point arithmetic, a 256-entry LUT for the sigmoid, and 628 neurons per design, with multiple parallel processing elements and AXI-DMA host communication; dynamic partial reconfiguration (DPR) allows rapid adaptation between generations. Results show substantial speedups over CPU baselines, with FPGA performance advantages that grow for longer integration periods and larger populations, and improvements reported in the 20–28% range over an ARM core. The work demonstrates the viability of FPGAs for accelerating evolvable dynamic neural networks and outlines future directions for higher-level tooling, automated DPR workflows, and hardware-optimized CTRNN architectures to broaden adoption and compete with GPUs on energy efficiency and throughput.

Abstract

Neuroevolution is a powerful method of applying an evolutionary algorithm to refine the performance of artificial neural networks through natural selection; however, the fitness evaluation of these networks can be time-consuming and computationally expensive, particularly for continuous time recurrent neural networks (CTRNNs) that necessitate the simulation of differential equations. To overcome this challenge, field programmable gate arrays (FPGAs) have emerged as an increasingly popular solution, due to their high performance and low power consumption. Further, their ability to undergo dynamic and partial reconfiguration enables the extremely rapid evaluation of the fitness of CTRNNs, effectively addressing the bottleneck associated with conventional methods of evolvable hardware. By incorporating fitness evaluation directly upon the programmable logic of the FPGA, hyper-parallel evaluation becomes feasible, dramatically reducing the time required for assessment. This inherent parallelism of FPGAs accelerates the entire neuroevolutionary process by several orders of magnitude, facilitating faster convergence to an optimal solution. The work presented in this study demonstrates the potential of utilizing dynamic and partial reconfiguration on capable FPGAs as a powerful platform for neuroevolving dynamic neural networks.

Neuroevolving Electronic Dynamical Networks

TL;DR

The paper tackles the bottleneck of fitness evaluation in neuroevolution of continuous-time recurrent neural networks (CTRNNs), which require simulating time-evolving dynamics. It introduces a hardware-accelerated approach that embeds CTRNN evaluation on a Xilinx ZCU102 FPGA, using forward-Euler integration, 16-bit fixed-point arithmetic, a 256-entry LUT for the sigmoid, and 628 neurons per design, with multiple parallel processing elements and AXI-DMA host communication; dynamic partial reconfiguration (DPR) allows rapid adaptation between generations. Results show substantial speedups over CPU baselines, with FPGA performance advantages that grow for longer integration periods and larger populations, and improvements reported in the 20–28% range over an ARM core. The work demonstrates the viability of FPGAs for accelerating evolvable dynamic neural networks and outlines future directions for higher-level tooling, automated DPR workflows, and hardware-optimized CTRNN architectures to broaden adoption and compete with GPUs on energy efficiency and throughput.

Abstract

Neuroevolution is a powerful method of applying an evolutionary algorithm to refine the performance of artificial neural networks through natural selection; however, the fitness evaluation of these networks can be time-consuming and computationally expensive, particularly for continuous time recurrent neural networks (CTRNNs) that necessitate the simulation of differential equations. To overcome this challenge, field programmable gate arrays (FPGAs) have emerged as an increasingly popular solution, due to their high performance and low power consumption. Further, their ability to undergo dynamic and partial reconfiguration enables the extremely rapid evaluation of the fitness of CTRNNs, effectively addressing the bottleneck associated with conventional methods of evolvable hardware. By incorporating fitness evaluation directly upon the programmable logic of the FPGA, hyper-parallel evaluation becomes feasible, dramatically reducing the time required for assessment. This inherent parallelism of FPGAs accelerates the entire neuroevolutionary process by several orders of magnitude, facilitating faster convergence to an optimal solution. The work presented in this study demonstrates the potential of utilizing dynamic and partial reconfiguration on capable FPGAs as a powerful platform for neuroevolving dynamic neural networks.
Paper Structure (11 sections, 1 equation, 3 figures)

This paper contains 11 sections, 1 equation, 3 figures.

Table of Contents

  1. Introduction
  2. FPGAs
  3. CTRNNs
  4. Neuroevolution
  5. Accelerating Neurovolution with FPGAs
  6. Objectives
  7. Method
  8. Experimental Results
  9. FPGA versus ARM
  10. Discussion
  11. Conclusion

Figures (3)

  • Figure 1: Absolute performance between FPGA and ARM
  • Figure 2: Initial comparative performance between FPGA and ARM
  • Figure 3: Percentage Improvement of FPGA over ARM