Variability-Aware Approximate Circuit Synthesis via Genetic Optimization

TL;DR

This work tackles process-variation-induced timing violations in deep-submicron CMOS by introducing an automated, circuit-agnostic framework that synthesizes variability-aware approximate circuits. It builds variability-aware standard cell libraries calibrated to Intel 14nm FinFET data and uses a stochastic, DAG-based delay estimator together with a software-based error simulator to guide a multi-objective NSGA-II optimization toward reduced CPD and its variability while keeping $NMED$ small. Key contributions include the first variability-aware LVF standard cell libraries, a high-level stochastic CPD estimator, and a gate-level approximation framework that achieves CPD reductions up to $26.4\%$ with average $NMED$ around $5.3\times 10^{-3}$, eliminating timing guardbands across diverse benchmarks. The approach yields substantial reliability and performance gains, demonstrated on arithmetic circuits, image processing filters, and ML classifiers, with favorable comparisons to state-of-the-art approximation methods. Practically, this enables robust, low-guardband designs suitable for technology nodes with higher variability, improving yield and latency without sacrificing accuracy.

Abstract

One of the major barriers that CMOS devices face at nanometer scale is increasing parameter variation due to manufacturing imperfections. Process variations severely inhibit the reliable operation of circuits, as the operational frequency at the nominal process corner is insufficient to suppress timing violations across the entire variability spectrum. To avoid variability-induced timing errors, previous efforts impose pessimistic and performance-degrading timing guardbands atop the operating frequency. In this work, we employ approximate computing principles and propose a circuit-agnostic automated framework for generating variability-aware approximate circuits that eliminate process-induced timing guardbands. Variability effects are accurately portrayed with the creation of variation-aware standard cell libraries, fully compatible with standard EDA tools. The underlying transistors are fully calibrated against industrial measurements from Intel 14nm FinFET in which both electrical characteristics of transistors and variability effects are accurately captured. In this work, we explore the design space of approximate variability-aware designs to automatically generate circuits of reduced variability and increased performance without the need for timing guardbands. Experimental results show that by introducing negligible functional error of merely $5.3\times 10^{-3}$, our variability-aware approximate circuits can be reliably operated under process variations without sacrificing the application performance.

Figures (14)

• Figure 1: Worst-case error evaluation obtained from a 1000-point Monte-Carlo variability analysis for several arithmetic circuits, image processing benchmarks, and machine learning classifiers (see Section \ref{['sec:evaluation']}). The Normalized Mean Error Distance (NMED) error metric is used (see Section \ref{['sec:csim']}).
• Figure 2: Demonstrative motivational example of the different critical paths that may arise under process variations. Red points indicate the gate delay at random samples from each delay distribution (i.e., different process conditions). (a) A single degradation scenario may lead the critical path (CP) through the XNOR gate, whereas (b) another condition may generate a CP comprising the XOR gate.
• Figure 3: Motivational case study for approximating multiple paths. An 8-bit adder is considered. X-axis comprises different gates while Y-axis shows their probability density function (PDF) to appear at a critical path under different variation. In red the gates that belong at the critical path of the variability-agnostic (nominal) circuit, while in orange the gates that do not.
• Figure 4: The industry compact model for FinFET (BSIM-CMG) is carefully calibrated to reproduce Intel 14nm measurement data extracted from intel_data. SPICE simulations (using our calibrated models) achieve an excellent agreement with the measurement data for both nFinFET and pFinFET devices. The top figure (a) shows the validation for the case of $I_{ds}$-$V_{gs}$ at high and low $V_{ds}$ biases. The bottom figure (b) shows the validation for the case of $I_{ds}$-$V_{ds}$ at various $V_{gs}$ biases. Figure data were obtained from FinFET_var.
• Figure 5: Variability calibration of our FinFET compact model against Intel 14nm measurement data intel_data. The regression line obtained from Monte-Carlo SPICE simulations on the transistor model is in good agreement with the data from Intel variability measurements. Figure data were obtained from FinFET_var.