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SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA

Dario Padovano, Alessio Carpegna, Alessandro Savino, Stefano Di Carlo

TL;DR

SpikeExplorer addresses the challenge of configuring FPGA-based accelerators for Spiking Neural Networks under edge constraints by performing hardware-oriented, multi-objective design space exploration. It combines a modular Python framework, snnTorch-based network modeling, SPIKER+-based hardware characterization, and a Bayesian optimization engine (AxClient) to search architectures, neuron models, and training parameters across power, area, latency, and accuracy objectives. The approach yields Pareto-optimal configurations demonstrated on MNIST, SHD, and DVS128, including a MNIST result of 95.8% accuracy with 180 mW per image and 0.12 ms per image latency. By automating co-processor design for neuromorphic edge applications, SpikeExplorer offers a practical tool to accelerate deployment of energy-efficient SNNs on embedded hardware.

Abstract

One of today's main concerns is to bring Artificial Intelligence power to embedded systems for edge applications. The hardware resources and power consumption required by state-of-the-art models are incompatible with the constrained environments observed in edge systems, such as IoT nodes and wearable devices. Spiking Neural Networks (SNNs) can represent a solution in this sense: inspired by neuroscience, they reach unparalleled power and resource efficiency when run on dedicated hardware accelerators. However, when designing such accelerators, the amount of choices that can be taken is huge. This paper presents SpikExplorer, a modular and flexible Python tool for hardware-oriented Automatic Design Space Exploration to automate the configuration of FPGA accelerators for SNNs. Using Bayesian optimizations, SpikerExplorer enables hardware-centric multi-objective optimization, supporting factors such as accuracy, area, latency, power, and various combinations during the exploration process. The tool searches the optimal network architecture, neuron model, and internal and training parameters, trying to reach the desired constraints imposed by the user. It allows for a straightforward network configuration, providing the full set of explored points for the user to pick the trade-off that best fits the needs. The potential of SpikExplorer is showcased using three benchmark datasets. It reaches 95.8% accuracy on the MNIST dataset, with a power consumption of 180mW/image and a latency of 0.12 ms/image, making it a powerful tool for automatically optimizing SNNs.

SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA

TL;DR

SpikeExplorer addresses the challenge of configuring FPGA-based accelerators for Spiking Neural Networks under edge constraints by performing hardware-oriented, multi-objective design space exploration. It combines a modular Python framework, snnTorch-based network modeling, SPIKER+-based hardware characterization, and a Bayesian optimization engine (AxClient) to search architectures, neuron models, and training parameters across power, area, latency, and accuracy objectives. The approach yields Pareto-optimal configurations demonstrated on MNIST, SHD, and DVS128, including a MNIST result of 95.8% accuracy with 180 mW per image and 0.12 ms per image latency. By automating co-processor design for neuromorphic edge applications, SpikeExplorer offers a practical tool to accelerate deployment of energy-efficient SNNs on embedded hardware.

Abstract

One of today's main concerns is to bring Artificial Intelligence power to embedded systems for edge applications. The hardware resources and power consumption required by state-of-the-art models are incompatible with the constrained environments observed in edge systems, such as IoT nodes and wearable devices. Spiking Neural Networks (SNNs) can represent a solution in this sense: inspired by neuroscience, they reach unparalleled power and resource efficiency when run on dedicated hardware accelerators. However, when designing such accelerators, the amount of choices that can be taken is huge. This paper presents SpikExplorer, a modular and flexible Python tool for hardware-oriented Automatic Design Space Exploration to automate the configuration of FPGA accelerators for SNNs. Using Bayesian optimizations, SpikerExplorer enables hardware-centric multi-objective optimization, supporting factors such as accuracy, area, latency, power, and various combinations during the exploration process. The tool searches the optimal network architecture, neuron model, and internal and training parameters, trying to reach the desired constraints imposed by the user. It allows for a straightforward network configuration, providing the full set of explored points for the user to pick the trade-off that best fits the needs. The potential of SpikExplorer is showcased using three benchmark datasets. It reaches 95.8% accuracy on the MNIST dataset, with a power consumption of 180mW/image and a latency of 0.12 ms/image, making it a powerful tool for automatically optimizing SNNs.
Paper Structure (19 sections, 7 equations, 7 figures, 6 tables)

This paper contains 19 sections, 7 equations, 7 figures, 6 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Network architecture
  4. Neuron models
  5. Training
  6. Automatic Design Space Exploration
  7. Related works
  8. Materials and Methods
  9. Network Generator and hardware neurons
  10. Area
  11. Accuracy and latency
  12. Power
  13. DSE engine
  14. Experimental results
  15. Experimental set-up
  16. ...and 4 more sections

Figures (7)

  • Figure 1: Design Space: (a) different network architectures; (b) different neuron models; (c) different surrogate functions and learning parameters
  • Figure 2: SpikeExplorer general architectures, including (i) a library of hardware neurons, (ii) a network evaluator estimating the performance of selected implementations, and (iii) a Bayesian engine.
  • Figure 3: Metrics estimation
  • Figure 4: Summarized code of spike explorer
  • Figure 5: Pareto frontiers of the global exploration on the three benchmark datasets targeting power, area, and accuracy optimization
  • ...and 2 more figures