Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices
Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari
TL;DR
The paper addresses the need for integrated functional and power-aware simulation for RISC-V by introducing an open-source framework that couples GVSoC, a RISC-V ISS, with SystemC-AMS for detailed power modeling. It presents a bus-centric architecture, defines integration requirements, and demonstrates a battery-powered audio DSP virtual prototype to enable Design Space Exploration. The results show that the framework supports fine-grained power analysis with acceptable overhead and enables actionable optimizations for battery lifetime. This work enables early, power-aware design iterations for battery-operated embedded devices, reducing development time and enabling richer multi-domain exploration.
Abstract
RISC-V cores have gained a lot of popularity over the last few years. However, being quite a recent and novel technology, there is still a gap in the availability of comprehensive simulation frameworks for RISC-V that cover both the functional and extra-functional aspects. This gap hinders progress in the field, as fast yet accurate system-level simulation is crucial for Design Space Exploration (DSE). This work presents an open-source framework designed to tackle this challenge, integrating functional RISC-V simulation (achieved with GVSoC) with SystemC-AMS (used to model extra-functional aspects, in detail power storage and distribution). The combination of GVSoC and SystemC-AMS in a single simulation framework allows to perform a DSE that is dependent on the mutual impact between functional and extra-functional aspects. In our experiments, we validate the framework's effectiveness by creating a virtual prototype of a compact, battery-powered embedded system.