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DE-HNN: An effective neural model for Circuit Netlist representation

Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Donghyeon Koh, Michael Defferrard, Elahe Rezaei, Ryan Carey, Rhett Davis, Rajeev Jain, Yusu Wang

TL;DR

The paper tackles the bottleneck of post-routing design feedback by predicting routing properties directly from input netlists. It introduces DE-HNN, a universal-approximation–capable neural network for directed hypergraphs, augmented with a hierarchical virtual-node scheme and persistence-based structural encodings to capture long-range interactions in massive netlists. Theoretical results establish the model's ability to approximate nested-permutation invariant functions on directed hypergraphs, and empirical evaluations on 12 large Superblue circuits show DE-HNN outperforms state-of-the-art baselines on HPWL, net-demand, and congestion prediction. The work also provides public netlists and benchmarks, highlighting practical impact for accelerating chip-design optimization and enabling robust ML studies of long-range graph interactions.

Abstract

The run-time for optimization tools used in chip design has grown with the complexity of designs to the point where it can take several days to go through one design cycle which has become a bottleneck. Designers want fast tools that can quickly give feedback on a design. Using the input and output data of the tools from past designs, one can attempt to build a machine learning model that predicts the outcome of a design in significantly shorter time than running the tool. The accuracy of such models is affected by the representation of the design data, which is usually a netlist that describes the elements of the digital circuit and how they are connected. Graph representations for the netlist together with graph neural networks have been investigated for such models. However, the characteristics of netlists pose several challenges for existing graph learning frameworks, due to the large number of nodes and the importance of long-range interactions between nodes. To address these challenges, we represent the netlist as a directed hypergraph and propose a Directional Equivariant Hypergraph Neural Network (DE-HNN) for the effective learning of (directed) hypergraphs. Theoretically, we show that our DE-HNN can universally approximate any node or hyperedge based function that satisfies certain permutation equivariant and invariant properties natural for directed hypergraphs. We compare the proposed DE-HNN with several State-of-the-art (SOTA) machine learning models for (hyper)graphs and netlists, and show that the DE-HNN significantly outperforms them in predicting the outcome of optimized place-and-route tools directly from the input netlists. Our source code and the netlists data used are publicly available at https://github.com/YusuLab/chips.git

DE-HNN: An effective neural model for Circuit Netlist representation

TL;DR

The paper tackles the bottleneck of post-routing design feedback by predicting routing properties directly from input netlists. It introduces DE-HNN, a universal-approximation–capable neural network for directed hypergraphs, augmented with a hierarchical virtual-node scheme and persistence-based structural encodings to capture long-range interactions in massive netlists. Theoretical results establish the model's ability to approximate nested-permutation invariant functions on directed hypergraphs, and empirical evaluations on 12 large Superblue circuits show DE-HNN outperforms state-of-the-art baselines on HPWL, net-demand, and congestion prediction. The work also provides public netlists and benchmarks, highlighting practical impact for accelerating chip-design optimization and enabling robust ML studies of long-range graph interactions.

Abstract

The run-time for optimization tools used in chip design has grown with the complexity of designs to the point where it can take several days to go through one design cycle which has become a bottleneck. Designers want fast tools that can quickly give feedback on a design. Using the input and output data of the tools from past designs, one can attempt to build a machine learning model that predicts the outcome of a design in significantly shorter time than running the tool. The accuracy of such models is affected by the representation of the design data, which is usually a netlist that describes the elements of the digital circuit and how they are connected. Graph representations for the netlist together with graph neural networks have been investigated for such models. However, the characteristics of netlists pose several challenges for existing graph learning frameworks, due to the large number of nodes and the importance of long-range interactions between nodes. To address these challenges, we represent the netlist as a directed hypergraph and propose a Directional Equivariant Hypergraph Neural Network (DE-HNN) for the effective learning of (directed) hypergraphs. Theoretically, we show that our DE-HNN can universally approximate any node or hyperedge based function that satisfies certain permutation equivariant and invariant properties natural for directed hypergraphs. We compare the proposed DE-HNN with several State-of-the-art (SOTA) machine learning models for (hyper)graphs and netlists, and show that the DE-HNN significantly outperforms them in predicting the outcome of optimized place-and-route tools directly from the input netlists. Our source code and the netlists data used are publicly available at https://github.com/YusuLab/chips.git
Paper Structure (27 sections, 4 theorems, 18 equations, 5 figures, 13 tables)

This paper contains 27 sections, 4 theorems, 18 equations, 5 figures, 13 tables.

Table of Contents

  1. Introduction
  2. Modeling netlists as directed hypergraphs
  3. Circuit netlists.
  4. DE-HNN: a neural network for directed hypergraphs
  5. Base-DE-HNN
  6. Theoretical analysis of DE-HNN
  7. Augmenting base-DE-HNN to DE-HNN
  8. Hierarchy of virtual nodes.
  9. Initial positional / structural encodings.
  10. Experiments
  11. Datasets
  12. Setup
  13. Baselines.
  14. Results
  15. Conclusion
  16. ...and 12 more sections

Key Result

Theorem 1

Let ${\mathcal{F}}$ be any continuous, nested-permutation invariant, net-value function as in Eqn (eq:M). For simplicity, assume both input nets and output of $M$ take values in a compact set $\mathcal{B} \subset \mathbb{R}^d$, a connected compact subset of $\mathbb{R}^d$. Then we have that ${\mathc where $\phi_1: \mathbb{R}^d \rightarrow \mathbb{R}^{d^{\prime}}$, $\phi_2: \mathbb{R}^{d^{\prime}}

Figures (5)

  • Figure 1: (a) A netlist with $7$ cells ${\mathcal{C}} = \{{\mathsf{c}}_1, \ldots, {\mathsf{c}}_7\}$ and 5 nets. For example, the output of gate $c_2$ flows into cells $c_3, c_5,$ and $c_7$, giving rise to the net ${\sigma} = (c_2, \{c_3,c_5, c_7\})$. That is, the driver cell of ${\sigma}$ is ${\mathsf{v}}_{{\sigma}} = c_2$, while its sink-set being ${\mathsf{S}}_{\sigma} = \{c_3, c_5, c_7\}$. (b) The corresponding directed hypergraph with $7$ nodes and $5$ hyperedges. Each node $v_i$ corresponds to cell ${\mathsf{c}}_i$, and each hyperedge is marked as a shaded region.
  • Figure 2: A two-level hierarchy of virtual nodes (VNs).
  • Figure 3: Ablation study for net-based demand regression (left, RMSE) and cell-based congestion classification (right, F-score).
  • Figure 4: Visulization of a circuit netlits in the post place-and-route stage: Each cell ($c_i$) is positioned within the physical layout of the chip and interconnected with other components following the net maps ($\sigma_i$).
  • Figure 5: Net-based wirelength, net-based demand and cell-based congestion distributions of each design.

Theorems & Definitions (8)

  • Theorem 1: Simplified
  • Proposition 1
  • proof
  • Lemma 1
  • proof
  • Remark 1
  • Theorem 1: Detailed
  • proof