A noise-tolerant, resource-saving probabilistic binary neural network implemented by the SOT-MRAM compute-in-memory system

TL;DR

This work provides a compelling framework for the design of reliable neural networks tailored to the applications with low power consumption and limited computational resources.

Abstract

We report a spin-orbit torque(SOT) magnetoresistive random-access memory(MRAM)-based probabilistic binary neural network(PBNN) for resource-saving and hardware noise-tolerant computing applications. With the presence of thermal fluctuation, the non-destructive SOT-driven magnetization switching characteristics lead to a random weight matrix with controllable probability distribution. In the meanwhile, the proposed CIM architecture allows for the concurrent execution of the probabilistic vector-matrix multiplication (PVMM) and binarization. Furthermore, leveraging the effectiveness of random binary cells to propagate multi-bit probabilistic information, our SOT-MRAM-based PBNN system achieves a 97.78\% classification accuracy under a 7.01\% weight variation on the MNIST database through 10 sampling cycles, and the number of bit-level computation operations is reduced by a factor of 6.9 compared to that of the full-precision LeNet-5 network. Our work provides a compelling framework for the design of reliable neural networks tailored to the applications with low power consumption and limited computational resources.

Figures (10)

• Figure 1: Schematic of the layer in probabilistic binary neuron networks.
• Figure 2: Proposed PBNN framework for the MNIST test where the network consists of 2$\times$ Convolution Layers (Convs), 2$\times$ Max Pooling Layers (MPs), 3$\times$ Fully Connected Layers (FCLs) and the Softmax Layer.
• Figure 3: (a). MNIST training results versus epoch times among different networks (b). Comparison of the classification accuracy between BNN and PBNN against weight variation.
• Figure 4: (a). The tunnel magneto-resistance of the in-plane SOT-MRAM device at room temperature. (b). Measured switching probability curve of the SOT-MRAM cell versus the write voltage ($V_{wr}$). The statistical probability at each point was obtained after 500 sampling cycles.
• Figure 5: Hardware Implementation of the SOT-MRAM-based PBNN system. (a). Circuit Schematic of the SOT-MRAM CIM module. (b). Input voltage patterns in reference to different operation modes of the bit-cell. (c). Operation waveforms of the PBNN CIM chip.