Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Testing Resource Isolation for System-on-Chip Architectures

Philippe Ledent, Radu Mateescu, Wendelin Serwe

TL;DR

This paper illustrates the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario using the industrial standard PSS and an academic approach based on conformance testing.

Abstract

Ensuring resource isolation at the hardware level is a crucial step towards more security inside the Internet of Things. Even though there is still no generally accepted technique to generate appropriate tests, it became clear that tests should be generated at the system level. In this paper, we illustrate the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario. We present both aspects using the industrial standard PSS and an academic approach based on conformance testing.

Testing Resource Isolation for System-on-Chip Architectures

TL;DR

This paper illustrates the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario using the industrial standard PSS and an academic approach based on conformance testing.

Abstract

Ensuring resource isolation at the hardware level is a crucial step towards more security inside the Internet of Things. Even though there is still no generally accepted technique to generate appropriate tests, it became clear that tests should be generated at the system level. In this paper, we illustrate the modeling aspects in test generation for resource isolation, namely modeling the behavior and expressing the intended test scenario. We present both aspects using the industrial standard PSS and an academic approach based on conformance testing.
Paper Structure (14 sections, 7 figures)

This paper contains 14 sections, 7 figures.

Table of Contents

  1. Introduction
  2. Modeling the SoC Behavior for Resource Isolation
  3. SoC Behavior Modeling in LNT
  4. SoC Behavior Modeling in PSS
  5. Test Generation from Test Scenarios
  6. Test Scenario 1: Reject for any Reason
  7. Test Scenario 2: Test all Possible Responses (Interleaving Semantics)
  8. Test Scenario 3: Test all Possible Responses (Sequential Semantics)
  9. Test Scenario 4: Access Data with Different Protection
  10. Conclusion
  11. LNT Model
  12. PSS Model
  13. Monolithic PSS Model
  14. SVL Script for all Verification Steps

Figures (7)

  • Figure 1: Symbolic automata representation of source (left) and target (right) behaviors
  • Figure 2: LNT process of a target
  • Figure 3: Action for granting a read request in the monolithic PSS model
  • Figure 4: Test scenario 1 ("reject for any reason") as TP in LNT (left) and VI in PSS (right)
  • Figure 5: Test scenario 2 ("all possible responses" interleaved) as TP in LNT (left) and VI in PSS (right)
  • ...and 2 more figures