FPGA-Based Neural Thrust Controller for UAVs

TL;DR

This work proposes a novel hardware board equipped with an Artix-7 FPGA for a popular open-source micro-UAV platform, and successfully validate its functionality by implementing an RL-based low-level controller using real-world experiments.

Abstract

The advent of unmanned aerial vehicles (UAVs) has improved a variety of fields by providing a versatile, cost-effective and accessible platform for implementing state-of-the-art algorithms. To accomplish a broader range of tasks, there is a growing need for enhanced on-board computing to cope with increasing complexity and dynamic environmental conditions. Recent advances have seen the application of Deep Neural Networks (DNNs), particularly in combination with Reinforcement Learning (RL), to improve the adaptability and performance of UAVs, especially in unknown environments. However, the computational requirements of DNNs pose a challenge to the limited computing resources available on many UAVs. This work explores the use of Field Programmable Gate Arrays (FPGAs) as a viable solution to this challenge, offering flexibility, high performance, energy and time efficiency. We propose a novel hardware board equipped with an Artix-7 FPGA for a popular open-source micro-UAV platform. We successfully validate its functionality by implementing an RL-based low-level controller using real-world experiments.

Figures (5)

• Figure 1: LF-deck with 4 IR receivers (marked in yellow), an Artix-7 FPGA XC7A15T (marked in light blue), one JTAG interface (marked in red) and an interface for connecting the deck with the Crazyflie (marked in white).
• Figure 2: Block diagram of the FPGA implementation. The base function refers to the functionality provided by the LF-deck suggested in taffanel2021lighthouse. Additionally, a combination of a MicroBlaze softcore processor and a hardware accelerator is provided, where the hardware accelerator is created at compilation time using a tool called PIRANHA.
• Figure 3: Integration into GCC and workflow of PIRANHA. This process identifies segments of the code that can be accelerated using a hardware accelerator.
• Figure 4: The neural network structure implemented in the work. The network consists of the self encoder $\boldsymbol{E}^q$ and the neighbor encoder $\boldsymbol{E}^k$. The neighbor encoder consists of the MLP $\boldsymbol{B}$ and a mean operator for calculating the mean vector $\boldsymbol{e}^k$ out of the output vectors of $\boldsymbol{B}$. The output of both encoders are concatenated, where $[ \boldsymbol{e}^q, \boldsymbol{e}^k ]$ denotes the concatenation, and processed in the output network $\boldsymbol{H}$.
• Figure 5: Flight trajectories of the Crazyflie, where the gray dashed line and blue line are the desired flight trajectory and the real flight trajectory respectively. a) 4 setpoints in different direction. b) Rectangular flight trajectory tracking. c) Spiral flight trajectory tracking.