Mapping Image Transformations Onto Pixel Processor Arrays

TL;DR

How various image transformations, including shearing, rotation and scaling, can be performed directly upon a PPA is demonstrated, using the SCAMP-5 vision chip, that contains a 256x256 pixel-parallel array.

Abstract

Pixel Processor Arrays (PPA) present a new vision sensor/processor architecture consisting of a SIMD array of processor elements, each capable of light capture, storage, processing and local communication. Such a device allows visual data to be efficiently stored and manipulated directly upon the focal plane, but also demands the invention of new approaches and algorithms, suitable for the massively-parallel fine-grain processor arrays. In this paper we demonstrate how various image transformations, including shearing, rotation and scaling, can be performed directly upon a PPA. The implementation details are presented using the SCAMP-5 vision chip, that contains a 256x256 pixel-parallel array. Our approaches for performing the image transformations efficiently exploit the parallel computation in a cellular processor array, minimizing the number of SIMD instructions required. These fundamental image transformations are vital building blocks for many visual tasks. This paper aims to serve as a reference for future PPA research while demonstrating the flexibility of PPA architectures.

Figures (7)

• Figure 1: A Pixel Processor Array contains a SIMD array of processing elements (PEs), on a 2D grid, where each PE contains processing and local memory and is allocated to one pixel in the image.
• Figure 2: Overview of the SCAMP vision system. The control program is executed on the ARM M0 core, which instructs the SCAMP-5 massively-parallel SIMD processor array to carry out operations on image arrays. SCAMP-5 has 256x256 Processing Elements.
• Figure 3: The architecture of the SCAMP-5 Processing Element. A-F are analog registers, PIX is image sensor input, IN is a global input. S0-S6 are general-purpose binary registers. Rx are special-purpose registers. ALU executes transfers and arithmetic and logic operations, 'Blur' and 'Prop' are additional asynchronous hardware accelerators. FLAG is local activity register. NEWS provides 4-neighbour communications. SLCT and SREC provide array addressing and 'Event' unit enables sparse read-out.
• Figure 4: Illustration of performing three steps of a horizontal shear. The FLAG register (Left Column) determines along which PE rows data is shifted at each stage. The FLAG register content itself is also shifted upwards in-between each step. As data is repeatedly shifted along the flagged rows the image becomes sheared (Top-Right to Bottom-Right).
• Figure 5: Example of performing three consecutive shear operations upon an image stored upon SCAMP-5, resulting in an image rotation.