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Electron-Tunnelling-Noise Programmable Random Variate Accelerator for Monte Carlo Sampling

James T. Meech, Vasileios Tsoutsouras, Phillip Stanley-Marbell

TL;DR

This work presents a domain-specific accelerator for Monte Carlo sampling that leverages electron-tunneling noise sampled via an XADC and a LiteX-generated FemtoRV RISC-V soft processor on an FPGA to speed random variate generation. It introduces a Gaussian-mixture kernel-density framework and a Gaussian-to-Gaussian transform to produce arbitrary univariate distributions, implemented through a hardware-software co-design with a programmable variate accelerator. Across twelve benchmarks, the solution achieves an average speedup of $8.70\times$ and a median of $8.69\times$ over GSL RNG, with Wasserstein-distance metrics increasing by $1.48\times$ (average) and $1.41\times$ (median), driven by the dominant sampling cost. Temperature sensitivity of the noise source is characterized and mitigated, while the total system power remains around $1.983$ W, validating practical viability for FPGA-based Monte Carlo workloads. The approach demonstrates flexible, high-throughput sampling suitable for real-time uncertainty quantification on low-power FPGA platforms with broad distribution support via kernel-density representations.

Abstract

This article presents an electron tunneling noise programmable random variate accelerator for accelerating the sampling stage of Monte Carlo simulations. We used the LiteX framework to generate a FemtoRV imfc RISC-V instruction set soft processor and deploy it on a Digilent Arty-100T FPGA development board. The RISC-V soft processor augmented with our programmable random variate accelerator achieves an average speedup of 8.70 times and a median speedup of 8.68 times for a suite of twelve different benchmark applications when compared to GNU Scientific Library software random number generation. These speedups are achievable because the benchmarks spend an average of 90.0 % of their execution time generating random samples. The results of the Monte Carlo benchmark programs run over the programmable random variate accelerator have an average Wasserstein distance of 1.48 times and a median Wasserstein distance of 1.41 times that of the results produced by the GNU Scientific Library random number generators. The soft processor samples the electron tunneling noise source using the hardened XADC block in the FPGA. The flexibility of the LiteX framework allows for the deployment of any LiteX-supported soft processor with an electron tunneling noise programmable random variate accelerator on any LiteX-supported development board that contains an FPGA with an XADC.

Electron-Tunnelling-Noise Programmable Random Variate Accelerator for Monte Carlo Sampling

TL;DR

This work presents a domain-specific accelerator for Monte Carlo sampling that leverages electron-tunneling noise sampled via an XADC and a LiteX-generated FemtoRV RISC-V soft processor on an FPGA to speed random variate generation. It introduces a Gaussian-mixture kernel-density framework and a Gaussian-to-Gaussian transform to produce arbitrary univariate distributions, implemented through a hardware-software co-design with a programmable variate accelerator. Across twelve benchmarks, the solution achieves an average speedup of and a median of over GSL RNG, with Wasserstein-distance metrics increasing by (average) and (median), driven by the dominant sampling cost. Temperature sensitivity of the noise source is characterized and mitigated, while the total system power remains around W, validating practical viability for FPGA-based Monte Carlo workloads. The approach demonstrates flexible, high-throughput sampling suitable for real-time uncertainty quantification on low-power FPGA platforms with broad distribution support via kernel-density representations.

Abstract

This article presents an electron tunneling noise programmable random variate accelerator for accelerating the sampling stage of Monte Carlo simulations. We used the LiteX framework to generate a FemtoRV imfc RISC-V instruction set soft processor and deploy it on a Digilent Arty-100T FPGA development board. The RISC-V soft processor augmented with our programmable random variate accelerator achieves an average speedup of 8.70 times and a median speedup of 8.68 times for a suite of twelve different benchmark applications when compared to GNU Scientific Library software random number generation. These speedups are achievable because the benchmarks spend an average of 90.0 % of their execution time generating random samples. The results of the Monte Carlo benchmark programs run over the programmable random variate accelerator have an average Wasserstein distance of 1.48 times and a median Wasserstein distance of 1.41 times that of the results produced by the GNU Scientific Library random number generators. The soft processor samples the electron tunneling noise source using the hardened XADC block in the FPGA. The flexibility of the LiteX framework allows for the deployment of any LiteX-supported soft processor with an electron tunneling noise programmable random variate accelerator on any LiteX-supported development board that contains an FPGA with an XADC.
Paper Structure (17 sections, 5 equations, 7 figures, 2 tables, 3 algorithms)

This paper contains 17 sections, 5 equations, 7 figures, 2 tables, 3 algorithms.

Figures (7)

  • Figure 1: The steps required to perform a Black Scholes Monte Carlo simulation using a programmable random variate accelerator instead of a digital electronic processor diverge at the first abstraction level below the abstract Black Scholes application required by the user. The programmable random variate accelerator requires small changes at every level of the software and hardware stack to use electron tunneling noise to generate samples from parameterized probability distributions to run the Monte Carlo simulation.
  • Figure 2: The physics-based Gaussian random number generator circuit. Details of circuits such as the constant current light emitting diode driver circuit that produces the 15 V bias voltage are omitted here but available in avalanche-noise.
  • Figure 3: The low power Gaussian noise source printed circuit board. The printed circuit board consumes 1.62 mW of power in the on state and 32.4 nW in the off state avalanche-noise.
  • Figure 4: The low power Gaussian noise source printed circuit board connected to the XADC of an Artix-7 XC7A100T FPGA on a Digilent Arty development board. The microSD card PMOD stores .elf program files to be executed on the soft processor on the FPGA. LiteOS provides the functionality to compile C language programs to .elf files for the RISC-V Petitbateau soft processor liteos. The FPGA development board and noise source board combined consume approximately 1.983 W of power when sampling from a univariate Gaussian.
  • Figure 5: The programmable random variate accelerator can use a kernel density encoded as a list of means, standard deviations, and weights to randomly sample from the mixture of Gaussian distributions that makes up the kernel density.
  • ...and 2 more figures