Photonic-Electronic Integrated Circuits for High-Performance Computing and AI Accelerators

TL;DR

This paper addresses the growing demand for high-performance AI computing in the post-Moore era by evaluating photonic-electronic integrated circuits (PICs) as a scalable hardware platform. It surveys both digital and analog PIC-based approaches, detailing optical logic gates, reconfigurable PICs, and EPALU designs for digital AI acceleration, as well as programmable modulation, photonic tensor cores, and training strategies for analog ONNs. The authors analyze architectural considerations, workload mapping, and software-hardware co-design, highlighting memory, data movement, energy efficiency, noise robustness, and the potential of cross-layer optimization and EPDA. Collectively, the work outlines practical pathways and outstanding challenges toward scalable PIC-based accelerators for AI, emphasizing domain-specific architectures, on-chip training, and integrated software stacks to realize real-world impact.

Abstract

In recent decades, the demand for computational power has surged, particularly with the rapid expansion of artificial intelligence (AI). As we navigate the post-Moore's law era, the limitations of traditional electrical digital computing, including process bottlenecks and power consumption issues, are propelling the search for alternative computing paradigms. Among various emerging technologies, integrated photonics stands out as a promising solution for next-generation high-performance computing, thanks to the inherent advantages of light, such as low latency, high bandwidth, and unique multiplexing techniques. Furthermore, the progress in photonic integrated circuits (PICs), which are equipped with abundant photoelectronic components, positions photonic-electronic integrated circuits as a viable solution for high-performance computing and hardware AI accelerators. In this review, we survey recent advancements in both PIC-based digital and analog computing for AI, exploring the principal benefits and obstacles of implementation. Additionally, we propose a comprehensive analysis of photonic AI from the perspectives of hardware implementation, accelerator architecture, and software-hardware co-design. In the end, acknowledging the existing challenges, we underscore potential strategies for overcoming these issues and offer insights into the future drivers for optical computing.

Figures (13)

• Figure 1: Implementations of electro-optic logic gates. (a) Schematic diagram of E-O logic composed of passive and active optical components. During each clock cycle, electrical inputs are used to configure the logic circuit, while light carries out logic operations based on the transmission characteristic of the logic block. (b)-(d) Schematic of MRR-based AND/NAND, OR/NOR, and XOR/XNOR gates, as proposed in Ref tian2011proofzhang2010demonstration. In the diagram, the dotted line and the solid line represent MRRs functioning in the “block/pass” and “pass/block” modes, respectively. These configurations correspond to the outputs of '0' and '1' at the through port, given a logic '0' as the electrical input.
• Figure 2: Reconfigurable PICs for arbitrary combinational logic. (a). Optical micrograph and cross-sectional diagram of a reconfigurable MRR featuring two modulation mechanisms. The p-i-n junction is applied by RF signal for input encoding, while the microheater is connected to the low-speed DC signal for resonance mode reconfiguration qiu2014reconfigurable. (b)-(c) Schematic of a PIC architecture that enables the implementation of arbitrary combinational logic expressions based on reconfigurable optical switchs (ROSs).
• Figure 3: EPALU architecture for high-performance digital computing. (a) Schematic of electronic–photonic microprocessor with its building blocks and data path. (b) Schematic of an $n$-$2^n$ E-O decoder and $2^n$-$n$ O-E multiplexer feng2020wavelength, where $s_i$ refers to the electrical input signal. (c) Schematic of a 2-bit CPA using E-O logic ying2018silicon. (d) Layout of a 2-bit barrel shifter using microdisk add-drop switch array, and the optical datapath with $S = \text{'01'}$feng2022integrated. (e) The architecture of the WDM-based $N$-bit multifunctional processing unit consists of a $(p, g)$ generation unit (PGU), $n$ sets of $m$-bit optical carry propagation networks (OCPNs), and an array of photodetectors (PDs) along with a network of electronic multiplexer units (MUXU) and an electronic sum generation unit (SGU) ying2020electronic. With different input combinations, EPALU can perform various logic/arithmetic functions (right).
• Figure 4: Schematic of an artificial neuron with simple synaptic model.
• Figure 5: Modulation techniques of photonic-electronic devices on PICs. (a) Optical micrograph and the normalized transmission curve of a thermo-optic MZI. Each arm of the MZI incorporates a microheater as a phase shifter feng2022compact. While both arms can be used to modulate the output signal, typically, one is used to set the modulator output at the quadrature point for a high extinction ratio in monotonic modulation. (b) Schematics and micrographs of free-carrier effect-based modulators working in carrier-injection mode chen2009integrated, carrier-depletion mode wang2013optimization, and by the MOSCAP-driven tuning mechanism hiraki2017heterogeneously. (c) Top, optical micrograph of an MRR modulator loaded with 10 $\mu$m long 20-nm-thick Sb2S3 and doped silicon PIN heater. Bottom, normalized transmission spectra of MRR when switching between two phases of Sb2S3chen2023non.