Quantum-activated neural reservoirs on-chip open up large hardware security models for resilient authentication

TL;DR

The paper presents a CMOS-compatible on-chip quantum neural reservoir (QNR) built from GST phase-change material that achieves over $3\times 10^{12}$ nodes in a 1 cm$^2$ area, with readout power around $0.07$ nW per channel. This large-scale quantum reservoir enables a dictionary-free, RAM-based resilient authentication scheme using one-time keys (OTKs) generated from QNR responses and decoded by a software neural network, with validation performed by a training-free validation autoencoder. The authors demonstrate robust key generation and validation, reporting $>99.6\%$ reliability, $100\%$ user authentication accuracy, and $>10^{3}$-bit key capacity per cm$^2$ (scaling to $>2^{1104}$ keys with increased electrode counts), while showing mutual information between keys near $10^{-3}$ and resistance to cloning. The work offers a scalable, energy-efficient hardware security primitive suitable for IoT, smart grids, and other secure infrastructures, leveraging quantum-nucleation dynamics to impede inference and cloning attacks.

Abstract

Quantum artificial intelligence is a frontier of artificial intelligence research, pioneering quantum AI-powered circuits to address problems beyond the reach of deep learning with classical architectures. This work implements a large-scale quantum-activated recurrent neural network possessing more than 3 trillion hardware nodes/cm$^2$, originating from repeatable atomic-scale nucleation dynamics in an amorphous material integrated on-chip, controlled with 0.07 nW electric power per readout channel. Compared to the best-performing reservoirs currently reported, this implementation increases the scale of the network by two orders of magnitude and reduces the power consumption by six, reaching power efficiencies in the range of the human brain, dissipating 0.2 nW/neuron. When interrogated by a classical input, the chip implements a large-scale hardware security model, enabling dictionary-free authentication secure against statistical inference attacks, including AI's present and future development, even for an adversary with a copy of all the classical components available. Experimental tests report 99.6% reliability, 100% user authentication accuracy, and an ideal 50% key uniqueness. Due to its quantum nature, the chip supports a bit density per feature size area three times higher than the best technology available, with the capacity to store more than $2^{1104}$ keys in a footprint of 1 cm$^2$. Such a quantum-powered platform could help counteract the emerging form of warfare led by the cybercrime industry in breaching authentication to target small to large-scale facilities, from private users to intelligent energy grids.

Figures (7)

• Figure 1: QNR implementation and TEM characterization (a) Schematic diagram of a QNR chipset covering a 4-inch wafer area; (b) Image of manufactured chips on the wafer; (c) Picture of single QNR device wire bounded to a side-brazed dual in-line ceramic package; (d)-(f) HRTEM images of different regions of the as-deposited GST film on the chip and corresponding SAED patterns of regions with nanocrystalline phase.
• Figure 2: AFM measurement results (a) Schematic diagram of the device's setup; (b) Point-to-point Resistance-Voltage spatial maps of a (1$\ \mu$m$\times$1$\ \mu$m) chip area obtained at increasing applied bias $V$; (c) Resistance-Voltage curves (solid lines) of selected set points in the chosen area (inset, colored markers) for applied bias $V$ between 0.2V and 1V. The color of each line indicates the evolution of the point marked with the same color in the inset; (d-f) Topography images of the selected area of the different applied bias $V$.
• Figure 3: High-Resolution TEM results HRTEM images and corresponding SAED patterns of GST film treated at (a) Room temperature, (b) 75 $^\circ C$, (c) 125 $^\circ C$, (d) 150 $^\circ C$, (e) 160 $^\circ C$, and (f) 170 $^\circ C$. We highlighted in red the portion of the sample showing quantum nucleated areas with crystalline phases.
• Figure 4: Data-drive model of the QNR response (a) Schematic diagram of the QNR chip with a set of input $x_p$ and output $y_q$ electrodes applied to the amorphous phase change material with random nonlinear resistivity distribution versus applied voltage (colormap) measured in Fig.\ref{['AFM']}. (b) Nanoscale circuit equivalent to a single quantum-activated nanocircuit of the QNR of $8$ nm $\times$$8$ nm area; (c) Current response of two randomly selected points in the AFM map and their equivalent nonlinear current-voltage distribution retrieved from AFM ( markers) and theoretical curve (solid line). (d) Simulation results on a single nanocircuit of the panel (b) for a triangular input excitation and different sweep rates. (e) Network structure of the entire system of quantum-activated nanocircuits.
• Figure 5: proposed architectures of QNR-based user authentication pipeline (a) A RAM creates random associations between one-time keys (OTK) with no mutual information with each other and a set of challenges. (b) Probability distribution of mutual information in a set of 10000 keys created from physical noise. (c) Server authentication model and challenge-response authentication steps. The server challenges the hardware security primitive (d), comprising the QNR with a nonlinear readout decoder unit, authenticating the received key with a validation autoencoder (VA). The VA does not use a dictionary or store any challenge-response relationship in the RAM.