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Parasitic Circus:On the Feasibility of Golden Free PCB Verification

Maryam Saadat Safa, Patrick Schaumont, Shahin Tajik

TL;DR

This work assesses the feasibility of eliminating a physical golden sample and replacing it with a simulated golden signature obtained by the PCB design files, and demonstrates how the parasitic impedance of the PCB components plays a major role in reaching a successful verification.

Abstract

Printed circuit boards (PCBs) are an integral part of electronic systems. Hence, verifying their physical integrity in the presence of supply chain attacks (e.g., tampering and counterfeiting) is of utmost importance. Recently, tamper detection techniques grounded in impedance characterization of PCB's Power Delivery Network (PDN) have gained prominence due to their global detection coverage, non-invasive, and low-cost nature. Similar to other physical verification methods, these techniques rely on the existence of a physical golden sample for signature comparisons. However, having access to a physical golden sample for golden signature extraction is not feasible in many real-world scenarios. In this work, we assess the feasibility of eliminating a physical golden sample and replacing it with a simulated golden signature obtained by the PCB design files. By performing extensive simulation and measurements on an in-house designed PCB, we demonstrate how the parasitic impedance of the PCB components plays a major role in reaching a successful verification. Based on the obtained results and using statistical metrics, we show that we can mitigate the discrepancy between collected signatures from simulation and measurements.

Parasitic Circus:On the Feasibility of Golden Free PCB Verification

TL;DR

This work assesses the feasibility of eliminating a physical golden sample and replacing it with a simulated golden signature obtained by the PCB design files, and demonstrates how the parasitic impedance of the PCB components plays a major role in reaching a successful verification.

Abstract

Printed circuit boards (PCBs) are an integral part of electronic systems. Hence, verifying their physical integrity in the presence of supply chain attacks (e.g., tampering and counterfeiting) is of utmost importance. Recently, tamper detection techniques grounded in impedance characterization of PCB's Power Delivery Network (PDN) have gained prominence due to their global detection coverage, non-invasive, and low-cost nature. Similar to other physical verification methods, these techniques rely on the existence of a physical golden sample for signature comparisons. However, having access to a physical golden sample for golden signature extraction is not feasible in many real-world scenarios. In this work, we assess the feasibility of eliminating a physical golden sample and replacing it with a simulated golden signature obtained by the PCB design files. By performing extensive simulation and measurements on an in-house designed PCB, we demonstrate how the parasitic impedance of the PCB components plays a major role in reaching a successful verification. Based on the obtained results and using statistical metrics, we show that we can mitigate the discrepancy between collected signatures from simulation and measurements.
Paper Structure (22 sections, 3 equations, 8 figures, 3 tables)

This paper contains 22 sections, 3 equations, 8 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Power Delivery Network (PDN)
  4. The Impact of Component's Parasitic
  5. Impedance Characterization using Scattering Parameters
  6. Methodology
  7. Threat Model
  8. Dynamic Time Warping (DTW)
  9. Golden-free Tamper Detection Method
  10. Experimental Setup
  11. Device Under Test (DUT)
  12. Simulation Setup
  13. Measurement Setup
  14. Results
  15. Emulating Tamper Events
  16. ...and 7 more sections

Figures (8)

  • Figure 1: An illustration of the PCB's supply chain reveals the possible risks, such as hardware Trojans and counterfeit or recycled parts, that may be inserted at each stage of PCB’s supply chain.
  • Figure 2: (a) The equivalent circuit of the PDN of an electronic board mosavirik2023impedanceverif. (b) The amplitude of the impedance profile of an electronic board over frequency.
  • Figure 3: Impedance profile of an ideal and non-ideal capacitor in log scale.
  • Figure 4: Hardware signature extraction based on reflection method.
  • Figure 5: (a) PDN circuit model of the PCB. (b) The simulated $|S_{11}|$ displays the impedance contribution of each component. In each step, ranging from 1 to 4, one component is added.
  • ...and 3 more figures