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Optimal Layout Synthesis for Deep Quantum Circuits on NISQ Processors with 100+ Qubits

Irfansha Shaik, Jaco van de Pol

TL;DR

This work tackles the problem of optimal layout synthesis for deep quantum circuits on large NISQ processors by introducing a SAT-based encoding that uses parallel plans. The Two-Way Parallel SAT encoding schedules exactly one SWAP per time step while grouping CNOTs and permits bidirectional propagation of CNOT dependencies, enabling scalability to circuits with many SWAPs. It incorporates bridges and relaxed dependencies to further reduce SWAPs and supports incremental solving for optimal make-spans. The resulting open-source tool, Q-Synth2, achieves SWAP-optimal mappings for deep circuits on platforms up to 127 qubits, outperforming leading near-optimal tools by up to 100x and maintaining near-optimal circuit depth, thereby enabling practical, high-fidelity layouts for large quantum processors.

Abstract

Layout synthesis is mapping a quantum circuit to a quantum processor. SWAP gate insertions are needed for scheduling 2-qubit gates only on connected physical qubits. With the ever-increasing number of qubits in NISQ processors, scalable layout synthesis is of utmost importance. With large optimality gaps observed in heuristic approaches, scalable exact methods are needed. While recent exact and near-optimal approaches scale to moderate circuits, large deep circuits are still out of scope. In this work, we propose a SAT encoding based on parallel plans that apply 1 SWAP and a group of CNOTs at each time step. Using domain-specific information, we maintain optimality in parallel plans while scaling to large and deep circuits. From our results, we show the scalability of our approach which significantly outperforms leading exact and near-optimal approaches (up to 100x). For the first time, we can optimally map several 8, 14, and 16 qubit circuits onto 54, 80, and 127 qubit platforms with up to 17 SWAPs. While adding optimal SWAPs, we also report near-optimal depth in our mapped circuits.

Optimal Layout Synthesis for Deep Quantum Circuits on NISQ Processors with 100+ Qubits

TL;DR

This work tackles the problem of optimal layout synthesis for deep quantum circuits on large NISQ processors by introducing a SAT-based encoding that uses parallel plans. The Two-Way Parallel SAT encoding schedules exactly one SWAP per time step while grouping CNOTs and permits bidirectional propagation of CNOT dependencies, enabling scalability to circuits with many SWAPs. It incorporates bridges and relaxed dependencies to further reduce SWAPs and supports incremental solving for optimal make-spans. The resulting open-source tool, Q-Synth2, achieves SWAP-optimal mappings for deep circuits on platforms up to 127 qubits, outperforming leading near-optimal tools by up to 100x and maintaining near-optimal circuit depth, thereby enabling practical, high-fidelity layouts for large quantum processors.

Abstract

Layout synthesis is mapping a quantum circuit to a quantum processor. SWAP gate insertions are needed for scheduling 2-qubit gates only on connected physical qubits. With the ever-increasing number of qubits in NISQ processors, scalable layout synthesis is of utmost importance. With large optimality gaps observed in heuristic approaches, scalable exact methods are needed. While recent exact and near-optimal approaches scale to moderate circuits, large deep circuits are still out of scope. In this work, we propose a SAT encoding based on parallel plans that apply 1 SWAP and a group of CNOTs at each time step. Using domain-specific information, we maintain optimality in parallel plans while scaling to large and deep circuits. From our results, we show the scalability of our approach which significantly outperforms leading exact and near-optimal approaches (up to 100x). For the first time, we can optimally map several 8, 14, and 16 qubit circuits onto 54, 80, and 127 qubit platforms with up to 17 SWAPs. While adding optimal SWAPs, we also report near-optimal depth in our mapped circuits.
Paper Structure (14 sections, 8 equations, 7 figures, 4 tables, 1 algorithm)

This paper contains 14 sections, 8 equations, 7 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Layout Synthesis for Quantum Circuits
  4. Optimal Layout Synthesis as Planning
  5. Parallel Plans in Optimal Layout Synthesis
  6. Incremental SAT Solving
  7. Two-Way Parallel SAT encoding
  8. Additional Functionality
  9. Design Choices
  10. Experimental Evaluation
  11. Experiment Design
  12. Results
  13. Discussion
  14. Conclusion

Figures (7)

  • Figure 1: $3$-qubit Or circuit with $6$ CNOT gates.
  • Figure 2: Reduced Or circuit and a $3$-qubit linear platform.
  • Figure 3: Mapped Or-circuit with 2 additional SWAPs (optimal).
  • Figure 4: Final Mapped Or-circuit after inserting back single-qubit gates.
  • Figure 5: Mapping reduced circuit using a SWAP and a bridge gate.
  • ...and 2 more figures