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A Hybrid Delay Model for Interconnected Multi-Input Gates

Arman Ferdowsi, Matthias Függer, Josef Salzmann, Ulrich Schmid

TL;DR

This work addresses the challenge of predicting multi-input switching MIS delays in interconnected gates with high speed and reasonable accuracy. It develops thresholded first-order hybrid delay models for interconnected NOR and Muller C gates by augmenting a RC interconnect, deriving analytic delay formulas δ(Δ) parameterized by extremal MIS delays and an interconnect delay δ_min. The authors provide a practical parameterization procedure and validate predictions against SPICE across technologies, wire lengths, loads, and drive strengths, demonstrating surprisingly good MIS-delay accuracy and orders-of-magnitude faster simulation times than SPICE. The results enable fast dynamic timing analysis via discrete-event simulation while outlining future work to integrate drafting effects and broader gate types into the Involution Tool.

Abstract

Dynamic digital timing analysis is a less accurate but fast alternative to highly accurate but slow analog simulations of digital circuits. It relies on gate delay models, which allow the determination of input-to-output delays of a gate on a per-transition basis. Accurate delay models not only consider the effect of preceding output transitions here but also delay variations induced by multi-input switching (MIS) effects in the case of multi-input gates. Starting out from a first-order hybrid delay model for CMOS two-input NOR gates, we develop a hybrid delay model for Muller C gates and show how to augment these models and their analytic delay formulas by a first-order interconnect. Moreover, we conduct a systematic evaluation of the resulting modeling accuracy: Using SPICE simulations, we quantify the MIS effects on the gate delays under various wire lengths, load capacitances, and input strengths for two different CMOS technologies, comparing these results to the predictions of appropriately parameterized versions of our new gate delay models. Overall, our experimental results reveal that they capture all MIS effects with a surprisingly good accuracy despite being first-order only.

A Hybrid Delay Model for Interconnected Multi-Input Gates

TL;DR

This work addresses the challenge of predicting multi-input switching MIS delays in interconnected gates with high speed and reasonable accuracy. It develops thresholded first-order hybrid delay models for interconnected NOR and Muller C gates by augmenting a RC interconnect, deriving analytic delay formulas δ(Δ) parameterized by extremal MIS delays and an interconnect delay δ_min. The authors provide a practical parameterization procedure and validate predictions against SPICE across technologies, wire lengths, loads, and drive strengths, demonstrating surprisingly good MIS-delay accuracy and orders-of-magnitude faster simulation times than SPICE. The results enable fast dynamic timing analysis via discrete-event simulation while outlining future work to integrate drafting effects and broader gate types into the Involution Tool.

Abstract

Dynamic digital timing analysis is a less accurate but fast alternative to highly accurate but slow analog simulations of digital circuits. It relies on gate delay models, which allow the determination of input-to-output delays of a gate on a per-transition basis. Accurate delay models not only consider the effect of preceding output transitions here but also delay variations induced by multi-input switching (MIS) effects in the case of multi-input gates. Starting out from a first-order hybrid delay model for CMOS two-input NOR gates, we develop a hybrid delay model for Muller C gates and show how to augment these models and their analytic delay formulas by a first-order interconnect. Moreover, we conduct a systematic evaluation of the resulting modeling accuracy: Using SPICE simulations, we quantify the MIS effects on the gate delays under various wire lengths, load capacitances, and input strengths for two different CMOS technologies, comparing these results to the predictions of appropriately parameterized versions of our new gate delay models. Overall, our experimental results reveal that they capture all MIS effects with a surprisingly good accuracy despite being first-order only.
Paper Structure (18 sections, 6 theorems, 55 equations, 15 figures, 15 tables)

This paper contains 18 sections, 6 theorems, 55 equations, 15 figures, 15 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Multi-input switching (MIS) effects
  4. Digital dynamic timing analysis
  5. Starting Point: A Thresholded Hybrid Model for NOR Gates
  6. An Accurate Hybrid MIS Delay Model for Interconnected NOR Gates
  7. Interconnect extension
  8. Model parametrization
  9. Experimental accuracy evaluation
  10. Wire length
  11. Wire resistance and capacitance
  12. Load capacitance
  13. Input gate driving strength
  14. Other technologies
  15. An Accurate Hybrid MIS Delay Model for Interconnected Muller C Gates
  16. ...and 3 more sections

Key Result

Theorem 1

For any $0 \leq |\Delta| \leq \infty$, the output voltage trajectory functions of our model for rising input transitions are given by The output voltage trajectory functions for falling input transitions are given by where $a=\frac{\alpha_1+\alpha_2}{2R}$, $d=a+\Delta$, $\chi=d^2-4c'$, $c'=\frac{\alpha_2 \Delta}{2R}$, and $A=\frac{\alpha_2\Delta - aR(d- \sqrt{\chi})}{2R\sqrt{\chi}}$. The output

Figures (15)

  • Figure 1: MIS effects in the measured delay of a $15$nm technology CMOS NOR gate. $\Delta=t_B-t_A$ is the input separation time between effective signal transitions at the inputs $A$ and $B$.
  • Figure 2: Illustration of the thresholded hybrid system of an IDM channel, with a single input $i$ and output $o$. It comprises an (optional) pure delay shifter, producing $i_d$, and two ODEs governing some state signal $x(t)$ that is digitized by a threshold voltage comparator to produce $o$. The active ODE is selected by the current state of $i_d$, with mode switches that guarantee continuity of $x(t)$.
  • Figure 3: Transistor schematic and the resistor model of a CMOS NOR gate along with its augmented RC interconnect component.
  • Figure 4: Lumped models for wires.
  • Figure 5: Experimental setup.
  • ...and 10 more figures

Theorems & Definitions (9)

  • Theorem 1: Output voltage trajectories for the NOR gate ferdowsi2024faithful
  • Theorem 2: MIS delay functions for the NOR gate ferdowsi2024faithful
  • Corollary 1: MIS delay functions for the interconnect-augmented NOR gate
  • proof
  • Theorem 3: Model parametrization for interconnect-augmented NOR gates
  • proof
  • Theorem 4: MIS Delay functions for interconnected C gates
  • Theorem 5: Model parametrization for interconnect-augmented C gates
  • proof