MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications

TL;DR

MATADOR is presented, an automated boolean-to-silicon tool with GUI interface capable of implementing optimized accelerator design of the TM model onto SoC-FPGA for inference at the edge and makes use of the logic sharing that ensues from propositional overlap.

Abstract

System-on-Chip Field-Programmable Gate Arrays (SoC-FPGAs) offer significant throughput gains for machine learning (ML) edge inference applications via the design of co-processor accelerator systems. However, the design effort for training and translating ML models into SoC-FPGA solutions can be substantial and requires specialist knowledge aware trade-offs between model performance, power consumption, latency and resource utilization. Contrary to other ML algorithms, Tsetlin Machine (TM) performs classification by forming logic proposition between boolean actions from the Tsetlin Automata (the learning elements) and boolean input features. A trained TM model, usually, exhibits high sparsity and considerable overlapping of these logic propositions both within and among the classes. The model, thus, can be translated to RTL-level design using a miniscule number of AND and NOT gates. This paper presents MATADOR, an automated boolean-to-silicon tool with GUI interface capable of implementing optimized accelerator design of the TM model onto SoC-FPGA for inference at the edge. It offers automation of the full development pipeline: model training, system level design generation, design verification and deployment. It makes use of the logic sharing that ensues from propositional overlap and creates a compact design by effectively utilizing the TM model's sparsity. MATADOR accelerator designs are shown to be up to 13.4x faster, up to 7x more resource frugal and up to 2x more power efficient when compared to the state-of-the-art Quantized and Binary Deep Neural Network implementations.

Figures (8)

• Figure 1: Visualization of the Tsetlin Machine and its main components. (a) shows the clause voting mechanism that results in class sums and classification. (b) internals of the clause with the learning element Tsetlin Automata and propositional logic that knits it with input literals (equivalent of features).
• Figure 2: Following Fig. \ref{['fig:TM_overview']}, here we visualize the outcomes of partial clauses (PC via the propositional logic for different boolean actions of the automaton. (a,b) if boolean action is 0 then the corresponding literal can be excluded from clause computation on the other hand it needs to be included if the action is 1. (c) the include-excludes result in boolean expression for the incoming input.
• Figure 3: Boolean-to-Silicon Overview: The boolean expression from the include-exclude decisions of the automata, are often found to be similar within various clauses, and classes, as highlighted in the Tsetlin Machine Inference box. Logic sharing can be used to shrink the combination circuit arising from the TM model. The clauses are the basis from which the SoC-FPGA system is built.
• Figure 4: (a): Packetization of a MNIST datapoint in the processor of the SoC-FPGA. (b): A snippet of the full clause expressions generated by MATADOR after training the Tsetlin Machine on MNIST. The clauses are a 2D array of dimensions [number of classes][number of clauses].
• Figure 5: Block diagram of the generated MATADOR inference accelerator architecture.