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Alya towards Exascale: Optimal OpenACC Performance of the Navier-Stokes Finite Element Assembly on GPUs

Herbert Owen, Dominik Ernst, Thomas Gruber, Oriol Lemkuhl, Guillaume Houzeaux, Lucas Gasparino, Gerhard Wellein

TL;DR

This work addresses the challenge of delivering portable yet highly efficient performance for CPU and GPU architectures by optimizing the RHS assembly in Alya’s incompressible Navier–Stokes solver. Starting from a unified OpenACC port, the authors systematically apply restructuring, algorithmic specialization, and privatization, guided by roofline modeling, to unlock the GPU’s potential. The resulting GPU implementations achieve beyond 50× speedups (≈2.5 TFlops FP64 on an NVIDIA A100) and CPU gains of ≈5–10×, with energy efficiency improvements aligning with Green500 expectations. The study demonstrates that a carefully designed, partially specialized approach can deliver substantial performance while maintaining a degree of portability, and provides actionable insights for applying similar strategies to related kernels in Alya and other codes. The findings highlight the practical impact of combining code restructuring, compile-time specialization, and privatization to achieve exascale-relevant performance in GPU-accelerated CFD workloads.

Abstract

This paper addresses the challenge of providing portable and highly efficient code structures for CPU and GPU architectures. We choose the assembly of the right-hand term in the incompressible flow module of the High-Performance Computational Mechanics code Alya, which is one of the two CFD codes in the Unified European Benchmark Suite. Starting from an efficient CPU-code and a related OpenACC-port for GPUs we successively investigate performance potentials arising from code specialization, algorithmic restructuring and low-level optimizations. We demonstrate that only the combination of these different dimensions of runtime optimization unveils the full performance potential on the GPU and CPU. Roofline-based performance modelling is applied in this process and we demonstrate the need to investigate new optimization strategies if a classical roofline limit such as memory bandwidth utilization is achieved, rather than stopping the process. The final unified OpenACC-based implementation boosts performance by more than 50x on an NVIDIA A100 GPU (achieving approximately 2.5 TF/s FP64) and a further factor of 5x for an Intel Icelake based CPU-node (achieving approximately 1.0 TF/s FP64). The insights gained in our manual approach lays ground implementing unified but still highly efficient code structures for related kernels in Alya and other applications. These can be realized by manual coding or automatic code generation frameworks.

Alya towards Exascale: Optimal OpenACC Performance of the Navier-Stokes Finite Element Assembly on GPUs

TL;DR

This work addresses the challenge of delivering portable yet highly efficient performance for CPU and GPU architectures by optimizing the RHS assembly in Alya’s incompressible Navier–Stokes solver. Starting from a unified OpenACC port, the authors systematically apply restructuring, algorithmic specialization, and privatization, guided by roofline modeling, to unlock the GPU’s potential. The resulting GPU implementations achieve beyond 50× speedups (≈2.5 TFlops FP64 on an NVIDIA A100) and CPU gains of ≈5–10×, with energy efficiency improvements aligning with Green500 expectations. The study demonstrates that a carefully designed, partially specialized approach can deliver substantial performance while maintaining a degree of portability, and provides actionable insights for applying similar strategies to related kernels in Alya and other codes. The findings highlight the practical impact of combining code restructuring, compile-time specialization, and privatization to achieve exascale-relevant performance in GPU-accelerated CFD workloads.

Abstract

This paper addresses the challenge of providing portable and highly efficient code structures for CPU and GPU architectures. We choose the assembly of the right-hand term in the incompressible flow module of the High-Performance Computational Mechanics code Alya, which is one of the two CFD codes in the Unified European Benchmark Suite. Starting from an efficient CPU-code and a related OpenACC-port for GPUs we successively investigate performance potentials arising from code specialization, algorithmic restructuring and low-level optimizations. We demonstrate that only the combination of these different dimensions of runtime optimization unveils the full performance potential on the GPU and CPU. Roofline-based performance modelling is applied in this process and we demonstrate the need to investigate new optimization strategies if a classical roofline limit such as memory bandwidth utilization is achieved, rather than stopping the process. The final unified OpenACC-based implementation boosts performance by more than 50x on an NVIDIA A100 GPU (achieving approximately 2.5 TF/s FP64) and a further factor of 5x for an Intel Icelake based CPU-node (achieving approximately 1.0 TF/s FP64). The insights gained in our manual approach lays ground implementing unified but still highly efficient code structures for related kernels in Alya and other applications. These can be realized by manual coding or automatic code generation frameworks.
Paper Structure (21 sections, 3 figures, 5 tables)

This paper contains 21 sections, 3 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Finite Element Assembly in CFD
  3. Measurements and Machines
  4. Case Description
  5. CPU measurements details
  6. GPU measurement details
  7. Status Quo: Vectorized Data Structures
  8. CPU Path
  9. OpenACC/GPU path
  10. Improvements
  11. Restructuring: Intermediate Value Lifetime Optimizations
  12. Algorithmic Specialization
  13. GPU Results
  14. CPU Results
  15. Improvements: Privatization
  16. ...and 6 more sections

Figures (3)

  • Figure 1: Volume rendering of the flow over the Bolund cliff, the test benchmark data set used in this paper
  • Figure 2: Performance in mega elements per second (left axis) and wall time in ms (right axis, inverted) vs CPU core count excluding Alya's master process. Perfect scaling line extrapolated from 4 worker rocesses. Errorbars indicate the lowest, highest and median value out of three runs.
  • Figure 3: Roofline diagram of the GPU versions DRAM and L2/s. Measured bandwidths from cudabenches. Includes a lower roof of [7.4]TFlop/s due to the application instruction mix.