Learning-driven Physically-aware Large-scale Circuit Gate Sizing

TL;DR

This work proposes a learning-driven physically aware gate sizing framework to optimize timing performance on large-scale circuits efficiently and achieves higher-timing performance improvements in a faster way compared with the commercial gate sizing tool.

Abstract

Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.

Figures (9)

• Figure 1: Rich information (a) in optimization flow; (b) on timing paths; (c) on design layouts.
• Figure 2: The overall flow of our framework.
• Figure 3: Data representation in our work. "Or. Gate" and "Op. Gate" represent the original gate size and optimized gate size.
• Figure 4: An example of timing information aggregation on multiple paths.
• Figure 5: An example of physical information aggregation on multiple scaled layouts.

Theorems & Definitions (4)

• Definition 1: Gate-wise critical path
• Definition 2: Gate-wise path group
• Definition 3: Gate-wise worst negative slack
• Definition 4: Gate-wise total negative slack