Multi-qubit DC gates over an inhomogeneous array of quantum dots

Abstract

The prospect of large-scale quantum computation with an integrated chip of spin qubits is imminent as technology improves. This invites us to think beyond the traditional 2-qubit-gate framework and consider a naturally supported ``instruction set'' of multi-qubit gates. In this work, we systematically study such a family of multi-qubit gates implementable over an array of quantum dots by DC evolution. A useful representation of the computational Hamiltonian is proposed for a dot-array with strong spin-orbit coupling effects, distinctive $g$-factor tensors and varying interdot couplings. Adopting a perturbative treatment, we model a multi-qubit DC gate by the first-order dynamics in the qubit frame and develop a detailed formalism for decomposing the resulting gate, estimating and optimizing the coherent gate errors with appropriate local phase shifts for arbitrary array connectivity. Examples of such multi-qubit gates and their applications in quantum error correction and quantum algorithms are also explored, demonstrating their potential advantage in accelerating complex tasks and reducing overall errors.

Figures (6)

• Figure 1: (a) A classification diagram of quantum gates. While a general multi-qubit unitary in the outer ring can be composed from universal 2-qubit gates in the inner disk, only a small number of these gates are directly implementable. The set of naturally accessible gates is determined by the interaction Hamiltonian and forms a cone (the shaded fan) that extends beyond the 2-qubit limit into multi-qubit domain. For spin qubits in particular, we can distinguish the DC class and the AC class, with the familiar CZ and CNOT gate as the respective 2-qubit member. This work generalizes the CZ/CPhase gate to a broader set of primitive multi-qubit DC gates for spin qubits. (b) A schematic plot of the modeled spin-qubit quantum chip, which is composed of an inhomogeneous array of quantum dots with varying Zeeman splitting energies, quantization axes and interdot coupling strengths. Apart from the 2-qubit CPhase gates (in the blue rectangle), it is revealed that some multi-qubits gates (in green regions) can also be naturally implemented with high fidelity on such array.
• Figure 2: Two basic types of array topology: (a) stellar topology, (b) chain topology. The red dot in each graph marks the first qubit in the Hilbert space for the reduced array vector formula in Eq. \ref{['eq:lambda-stellar']} and Eq. \ref{['eq:lambda-linear']}. We also note that the array topology depends only one the way how the dots are directly coupled by exchange interaction, not by their relative position or distance.
• Figure 3: Decomposition of multi-qubit DC gates based on the interdot connectivity. (a) The DC gate for a 4-qubit system in stellar topology is an multi-qubit CPhase gate, which can be decomposed as the product of 3 regular CPhase gates. (b) The DC gate of a 3-qubit ring does not contain a control qubit, as the 3 qubits are totally symmetric to each other. (c) Two different ways of decomposing the same DC gate for a 6-qubits array as product of 2 MTCP gates. The resulting local phase corrections are independent of particular choice of decomposition.
• Figure 4: Benchmarking the $m$-qubit gate $\mathrm{CZ}_2\mathrm{Z}_3\cdots\mathrm{Z}_m$ with an equivalent circuit composed by $m$ applications of 2-qubit $\mathrm{CZ}$ gates. If only coherent errors are taken into account, multi-qubit gates suffer a slight performance hit compared to equivalent 2-qubit gates. If a small stochastic charge noise is considered, the multi-qubit gates will outperform significant fidelity advantages over 2-qubit gates. Under an optimal set of phase gauge determined in Eq. \ref{['eq:optimal-corr']} The errors for multi-qubit gates can be further effectively suppressed.
• Figure 5: Example demonstrations of simultaneous parity checks through MTCP gates. (a) The quantum circuit to perform parity check of the $Z_1Z_2$ operator. The circuit can also be slightly modified to perform parity check of the $X_1X_2$ operator. (b) A two-dimension parity check circuit that simultaneously check the parity of the four neighboring qubits by application of the $\mathrm{CZ}_1Z_2Z_3Z_4$ gate and measurement of the controlled qubit. (c) A basic unit cell of the surface code that involves data qubits with $X$ and $Z$ parity check maps. Both of these maps can be efficiently carried out using MTCP gates. (d) The circuit diagram of the surface code stabilizing cycle for the shared data qubit 1 and 2. The red and blue vertical lines joining three circuit wires are an application of $\mathrm{CZ}_1Z_2$ gates, with the control qubits $X$ and $Z$ as in (c).