The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming

TL;DR

Memristor-based on-chip training is hampered by non-linearity, asymmetry, and device variation. The authors train a neural-pulse predictor to convert desired conductance updates $ΔG$ into programming pulses, outputting the required time $t_{pulse}$ given the current conductance $G$, and they further refine this via history-guided mappings to $G_{output}$. In simulation and on-chip demonstrations, the approach achieves substantially reduced programming delays and, for many devices, near-target conductances within a single attempt (approximately 95% within ±50% of the target), enabling faster on-chip learning. This work points to a practical path for memristor-based accelerators by co-designing memristor tuning with neural predictors, reducing latency and hardware overhead while enabling parallel, in-situ training capabilities.

Abstract

Memristive devices hold promise to improve the scale and efficiency of machine learning and neuromorphic hardware, thanks to their compact size, low power consumption, and the ability to perform matrix multiplications in constant time. However, on-chip training with memristor arrays still faces challenges, including device-to-device and cycle-to-cycle variations, switching non-linearity, and especially SET and RESET asymmetry. To combat device non-linearity and asymmetry, we propose to program memristors by harnessing neural networks that map desired conductance updates to the required pulse times. With our method, approximately 95% of devices can be programmed within a relative percentage difference of +-50% from the target conductance after just one attempt. Our approach substantially reduces memristor programming delays compared to traditional write-and-verify methods, presenting an advantageous solution for on-chip training scenarios. Furthermore, our proposed neural network can be accelerated by memristor arrays upon deployment, providing assistance while reducing hardware overhead compared with previous works. This work contributes significantly to the practical application of memristors, particularly in reducing delays in memristor programming. It also envisions the future development of memristor-based machine learning accelerators.

Figures (8)

• Figure 1: The Ouroboros of Memristors: While memristors are typically utilized to bolster machine learning networks, our innovative approach leverages neural networks to streamline memristor programming, thereby amplifying on-chip training performance for upcoming memristor-based accelerators.
• Figure 2: (a): Illustration of the equivalent circuit diagram for the JART memristor model. (b): Simulation results depicting switching curves following the application of 6000 SET pulses and 6000 RESET pulses across 10 devices.
• Figure 3: (a) RPDs of $G_\text{output}$ generated by networks deployed in simulation and (b) the corresponding histograms. These networks underwent training from the ground up using MSE loss. The models were saved based on the best RPD of $t_\text{output}$ or $G_\text{output}$ observed on the validation dataset.
• Figure 4: RPDs plotted with $G_\text{start}$ and $G_\text{target}$ for the pulse predictors (a) trained from scratch with MSE loss, and (b) based on noise-free model.
• Figure 5: (a) Mapping of $G-t$ (kernel size 11, 101, and 1001 shifted for better visibility) and (b) the corresponding gradients in an example $G-t$ history. Various kernel sizes were employed during the smoothing process.