Towards Multiphase Clocking in Single-Flux Quantum Systems

Abstract

Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive electronics technologies. SFQ systems operate at tens of gigahertz with up to three orders of magnitude smaller power as compared to CMOS. In conventional SFQ systems, most gates require clock signal. Each gate should have the fanins with equal logic depth, necessitating insertion of path-balancing (PB) DFFs, incurring prohibitive area penalty. Multiphase clocking is the effective method for reducing the path-balancing overhead at the cost of reduced throughput. However, existing tools are not directly applicable for technology mapping of multiphase systems. To overcome this limitation, in this work, we propose a technology mapping tool for multiphase systems. Our contribution is threefold. First, we formulate a phase assignment as a Constraint Programming with Satisfiability (CP-SAT) problem, to determine the phase of each element within the network. Second, we formulate the path balancing problem as a CP-SAT to optimize the number of DFFs within an asynchronous datapath. Finally, we integrate these methods into a technology mapping flow to convert a logic network into a multiphase SFQ circuit. In our case studies, by using seven phases, the size of the circuit (expressed as the number of Josephson junctions) is reduced, on average, by 59.94 % as compared to the dual (fast-slow) clocking method, while outperforming the state-of-the-art single-phase SFQ mapping tools.

Figures (6)

• Figure 1: a) An example of a CMOS circuit. b) Equivalent SFQ circuit with a splitter and two path balancing DFFs. c) A four-phase SFQ realization with no path balancing DFFs. The numbers indicate the phase corresponding to each clocked gate.
• Figure 2: An example two-phase network. Each PI is placed at stage 0 or 1, at epoch 0. The POs are placed at stages 4 and 5, corresponding to epoch 2.
• Figure 3: The effect of phase assigned to splitters and mergers. Datapaths (a) and (b) execute the same function. The phases assigned to the splitters and mergers (denoted as $\mathtt{S}$ and $\mathtt{M}$, respectively) are however different. The potential DFF locations (depicted as yellow rectangles) are therefore different in the two datapaths.
• Figure 4: Timing constraints of an $\mathtt{SA}$ gate. a) The gate should be preceded by an $\mathtt{AS}$ gate at the same stage. b) Example of an invalid assignment. The $\mathtt{AS}$ gate is preceded by an $\mathtt{AA}$ gate at the same stage. c) The issue is resolved by shifting the $\mathtt{SA}$ gate to the next stage and inserting two path balancing DFFs.
• Figure 5: Example of an asynchronous datapath within a four-phase network ($n=4$). The black triangles, and black curved shapes represent the $\mathtt{AS}$ and $\mathtt{SA}$ elements, respectively. Red circles denote the $\mathtt{AA}$ elements. a) Three independent paths are drawn with red solid, black solid, and black dotted arrows. b) DFF sites shown as rectangles within the red independent path. The grey DFF sites represent the chain $\mathtt{Q}$ of length $n$. Diagonally shaded DFF sites precede the $\mathtt{SA}$ gates. DFFs should therefore be placed at these sites.