DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks

TL;DR

A generic LL enhancement method based on a randomized algorithm that can significantly decrease the correlation between locked circuit netlist and correct key values in an LL scheme and efficiently degrade the accuracy of state-of-the-art ML-based attacks.

Abstract

Logic locking (LL) has gained attention as a promising intellectual property protection measure for integrated circuits. However, recent attacks, facilitated by machine learning (ML), have shown the potential to predict the correct key in multiple LL schemes by exploiting the correlation of the correct key value with the circuit structure. This paper presents a generic LL enhancement method based on a randomized algorithm that can significantly decrease the correlation between locked circuit netlist and correct key values in an LL scheme. Numerical results show that the proposed method can efficiently degrade the accuracy of state-of-the-art ML-based attacks down to around 50%, resulting in negligible advantage versus random guessing.

Figures (12)

• Figure 1: The schematics of a simple circuit (a) before and (b) after being locked by XOR/XNOR-based insertion roy2010endingrajendran2013faultyasin2016improving.
• Figure 2: Flowchart of an ML-based attack.
• Figure 3: An example of feature vector extraction and encoding in SnapShotsisejkovic2020challenging and OMLAalrahis2021omla.
• Figure 4: (a) Many-to-one and (b) one-to-many mappings from features, associated with different locked circuit functions and netlist structures, to correct keys. Each cofactor in blue is equivalent to the original circuit function. Otherwise, the cofactor is in red.
• Figure 5: Functional models of (a) the intermediate locked circuit function $f_{int}$zhou2017humblehu2019models and (b) the locked circuit function $f_{l}$ after adding additional correct keys.